Abstract
We propose a novel power splitter (or divider) comprising two back-to-back quarter-wavelength (λ/4) coupled lines (i.e. coupler). To improve the isolation between the output ports (i.e. ports 2 and 3), an isolation resistor R is included. Three power dividers are designed and implemented. To enhance the reflection coefficients, and S21 and S31 and their amplitude imbalance (AI) and phase difference (PD), the output ports transmission lines (TLs) of the first power divider (i.e. divider-1) with R of 100 Ω adopt tapered width from 8 to 3 μm. For contrast, the second power divider (i.e. divider-2) with R of 100 Ω uses tapered width from 8 to 3 μm for the input port (i.e. port 1) TL. To study the effect of R on the performance of the power divider, the third power divider (i.e. divider-3) has the same layout with divider-2 except R equal to 50 Ω. Prominent results are obtained. For instance, divider-1 occupies a small chip area of 0.026 mm2 (i.e. 2.3 × 10−4λ 20 ), one of the smallest normalized chip areas ever reported for millimeter-wave power dividers. Moreover, at 33 GHz, divider-1 achieves excellent S11 of − 13.1 dB, S22 of − 14 dB, S33 of − 14.2 dB, and S32 of − 17.9 dB, S21 of − 4.22 dB, S31 of − 3.99 dB, AI of − 0.23 dB, and PD of 2.1°. The remarkable results of the proposed power divider structure indicate that it is suitable for Ka-band and even higher frequency transceivers.
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Acknowledgements
This work is supported by the Ministry of Science and Technology (MOST) of the R.O.C. under Contracts MOST108-2221-E-260-015-MY3 and MOST108-2221-E-260-016-MY3. The authors are very grateful for the support from Taiwan Semiconductor Research Institute (TSRI) for chip fabrication and RF measurements.
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Lin, YS., Yeh, BT. & Lan, KS. Design and implementation of coupler-based Ka-band CMOS power splitters. Analog Integr Circ Sig Process 108, 25–36 (2021). https://doi.org/10.1007/s10470-021-01801-6
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DOI: https://doi.org/10.1007/s10470-021-01801-6