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Determination of the Operating Time to Failure of a Sub-100-nm MOS Transistor Gate Dielectric Using Accelerated Tests
Russian Microelectronics Pub Date : 2021-01-27 , DOI: 10.1134/s1063739720070124
A. S. Sivchenko , E. V. Kuznetsov , A. N. Saurov

Abstract

A gate dielectric is one of the key structural elements of submicron MOS transistors, on which the reliability of its operation depends. A breakdown of the dielectric leads to a loss in the functioning of the transistor and the failure of the entire IC or a malfunction in its operation. Therefore, special attention is paid to assess the defectiveness of a gate dielectric and its operating time to failure. In this study, the operating time to failure of the gate insulator of MOS transistors is determined based on the method of the time-dependent breakdown of the dielectric using the thermomechanical model (E models). The Weibull distribution obtained for the integrated failure distribution of a sample of technological test structures measured at high voltage and temperature is used as the statistics of the distribution of failures. The studies are performed on the test structures, which are MOS capacitors with the gate dielectric thickness of 5 nm. The test structures are created using the 65 nm serial technology and are placed in a test crystal together with the IC on one plate. Software is developed that allows accelerated measurements in the automatic mode. As a result of the studies, the parameters of the thermomechanical failure model are determined, and the dependences of the operating time to failure of the gate dielectric on the operating conditions are obtained. It is established that for the test structures under study, both full and partial breakdown of the dielectric can occur. This control method can be used to predict the long-term reliability of the gate dielectric of sub-100-nm MOS transistors and certify the technological processes of its production.



中文翻译:

使用加速测试确定亚100 nm MOS晶体管栅介质的失效时间

摘要

栅极电介质是亚微米MOS晶体管的关键结构元素之一,其工作可靠性取决于其。电介质的击穿会导致晶体管功能的丧失和整个IC的故障或其工作故障。因此,要特别注意评估栅极电介质的缺陷及其失效的时间。在这项研究中,基于电介质随时间的击穿方法,使用热力学模型来确定MOS晶体管栅极绝缘体失效的工作时间(E楷模)。将在高压和高温下测量的技术测试结构样品的综合故障分布获得的威布尔分布用作故障分布的统计数据。研究是在测试结构上进行的,测试结构是栅极电介质厚度为5 nm的MOS电容器。测试结构使用65 nm串行技术创建,并与IC一起放在一块板上的测试晶体中。开发了允许在自动模式下加速测量的软件。作为研究的结果,确定了热机械故障模型的参数,并且获得了操作时间到栅极电介质的故障对操作条件的依赖性。已经确定,对于正在研究的测试结构,电介质的全部和部分击穿都可能发生。此控制方法可用于预测100纳米以下MOS晶体管的栅极电介质的长期可靠性,并验证其生产工艺。

更新日期:2021-01-28
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