Determination of the Operating Time to Failure of a Sub-100-nm MOS Transistor Gate Dielectric Using Accelerated Tests

Abstract

A gate dielectric is one of the key structural elements of submicron MOS transistors, on which the reliability of its operation depends. A breakdown of the dielectric leads to a loss in the functioning of the transistor and the failure of the entire IC or a malfunction in its operation. Therefore, special attention is paid to assess the defectiveness of a gate dielectric and its operating time to failure. In this study, the operating time to failure of the gate insulator of MOS transistors is determined based on the method of the time-dependent breakdown of the dielectric using the thermomechanical model (E models). The Weibull distribution obtained for the integrated failure distribution of a sample of technological test structures measured at high voltage and temperature is used as the statistics of the distribution of failures. The studies are performed on the test structures, which are MOS capacitors with the gate dielectric thickness of 5 nm. The test structures are created using the 65 nm serial technology and are placed in a test crystal together with the IC on one plate. Software is developed that allows accelerated measurements in the automatic mode. As a result of the studies, the parameters of the thermomechanical failure model are determined, and the dependences of the operating time to failure of the gate dielectric on the operating conditions are obtained. It is established that for the test structures under study, both full and partial breakdown of the dielectric can occur. This control method can be used to predict the long-term reliability of the gate dielectric of sub-100-nm MOS transistors and certify the technological processes of its production.