While scaling down the devices it is important not to compromise with the performance. Scaling of tunnel devices shows better performance than Field Effect Transistors (FETs). Charge Plasma based Dopingless Double Gate Tunnel Field Effect Transistor (DLDGTFET) with its various misaligned configurations are designed, discussed and analyzed in the presented work. Silicon is preferred as a choice of material. For various misalignment configurations, initially, bottom gate is shifted towards the right, then it is shifted towards left and at last bottom and top, both gates are misplaced for analyzing the device parameters, analog parameters and linearity parameters. By misalignment, it is observed that either the bottom gate is misaligned towards the right or left or both gates are being misaligned, device performance degraded. The basic structure shows the higher drain current, better drive current among other structures such as 15 μA. whereas source underlapped (SU100) structure shows the better subthreshold slope such as 20 mV/decade. But SU100 has the least amount of drive current. In the subthreshold region, BM100 has the maximum value of transconductance gain factor i.e. 10⁴ V⁻¹. When the bottom gate is shifted towards right i.e. for drain overlapped structure it was observed that it shows better linearity parameters and can be considered for low noise and low voltage applications.

在缩小设备尺寸时，重要的是不要牺牲性能。隧道器件的缩放比场效应晶体管（FET）显示出更好的性能。基于电荷等离子体的无掺杂双栅极隧道场效应晶体管（DLDGTFET）具有各种未对准的配置，在本文中进行了设计，讨论和分析。硅是优选的材料选择。对于各种失准配置，首先将底栅移至右侧，然后将其移至左侧，最后移至底部和顶部，将两个栅放错位置以分析设备参数，模拟参数和线性参数。通过失准，可以观察到底部栅极向右或向左失准，或者两个栅极均未对准，器件性能下降。基本结构显示出较高的漏极电流，更好的驱动电流，例如15μA。而源下重叠（SU100）结构显示出更好的亚阈值斜率，例如20 mV /十倍频程。但是SU100的驱动电流最少。在亚阈值区域，BM100具有跨导增益因子的最大值，即10 ⁴  V ^{- 1}。当底部栅极向右移动时，即对于漏极重叠结构，观察到它显示出更好的线性参数，可以考虑用于低噪声和低电压应用。