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Tweaking the Performance of Dopingless Nano-TFET with Misaligned Sandwiched Dual-Gate Structure

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Abstract

While scaling down the devices it is important not to compromise with the performance. Scaling of tunnel devices shows better performance than Field Effect Transistors (FETs). Charge Plasma based Dopingless Double Gate Tunnel Field Effect Transistor (DLDGTFET) with its various misaligned configurations are designed, discussed and analyzed in the presented work. Silicon is preferred as a choice of material. For various misalignment configurations, initially, bottom gate is shifted towards the right, then it is shifted towards left and at last bottom and top, both gates are misplaced for analyzing the device parameters, analog parameters and linearity parameters. By misalignment, it is observed that either the bottom gate is misaligned towards the right or left or both gates are being misaligned, device performance degraded. The basic structure shows the higher drain current, better drive current among other structures such as 15 μA. whereas source underlapped (SU100) structure shows the better subthreshold slope such as 20 mV/decade. But SU100 has the least amount of drive current. In the subthreshold region, BM100 has the maximum value of transconductance gain factor i.e. 104 V−1. When the bottom gate is shifted towards right i.e. for drain overlapped structure it was observed that it shows better linearity parameters and can be considered for low noise and low voltage applications.

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Acknowledgments

The Author wishes to thanks Dr. Ashish Raman for his work in the field of semiconductor devices. We also thanks to the VLSI design Lab., Department of Electronics and communications, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, 144011, India.

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No funding was received for conducting this study.

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Authors and Affiliations

  1. Department of Electronics and Communications, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, 144011, India

    Deep Shekhar & Ashish Raman

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  1. Deep Shekhar
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  2. Ashish Raman
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Contributions

All the authors contributed to the study conception and design, literature review, material preparation, simulation, and analysis were performed by [Deep Shekhar] and [Dr. Ashish Raman]. The final draft of the manuscript was written by [Deep Shekhar] and all authors commented on the previous version of the manuscripts. All authors read and approved the final manuscript.

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Correspondence to Deep Shekhar.

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No funding was received for conducting this study. Informed consent was obtained from all individual participants included in the study. The authors report no conflicts of interest. This article does not contain any studies with human or animal subjects.

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Shekhar, D., Raman, A. Tweaking the Performance of Dopingless Nano-TFET with Misaligned Sandwiched Dual-Gate Structure. Silicon 13, 3713–3723 (2021). https://doi.org/10.1007/s12633-021-00956-1

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