CMOS scaling is the approach to accomplish the VLSI goals in the past decades. The existing CMOS technology is facing challenges related to short channel effects and reached to its performance limits at sub-10 nm technology nodes. The negative capacitance field-effect transistor is a potential device for near future technology to overcome these challenges. In the present work, negative capacitance Junctionless (NC-JL) FinFET with Metal-Ferroelectric–Insulator-Semiconductor (MFIS) structure is proposed and analysed comprehensively using TCAD simulation for its scaling capability over the various technology nodes starting from 24 nm to 5 nm. It is revealed that the integration of negative capacitance (NC) with JL FinFET helps to reduce the leakage current, short channel effects such as subthreshold slope, DIBL and provide high drive current as well as fast switching by reducing intrinsic delay for extremely short channel length as compared to standard-JL FinFET. Furthermore, the different performance parameters including Gate Induced Drain Leakage Current (GIDL) of proposed NC-JL FinFET are comprehensively studied.

CMOS缩放是过去几十年来实现VLSI目标的方法。现有的CMOS技术正面临与短沟道效应相关的挑战，并已达到10纳米以下技术节点的性能极限。负电容场效应晶体管是在不久的将来克服这些挑战的潜在设备。在当前工作中，提出了具有金属-铁电-绝缘体-半导体（MFIS）结构的负电容无结（NC-JL）FinFET，并使用TCAD仿真对其进行了全面分析，以分析其在从24 nm到5 nm的各种技术节点上的缩放能力。结果表明，负电容（NC）与JL FinFET的集成有助于减少漏电流，短沟道效应，例如亚阈值斜率，与标准JL FinFET相比，DIBL可以通过减少固有延迟来提供极高的驱动电流以及快速切换，从而大大缩短了沟道长度。此外，还对所提出的NC-JL FinFET的不同性能参数（包括栅极感应漏极漏电流（GIDL））进行了综合研究。