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Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling

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Abstract

CMOS scaling is the approach to accomplish the VLSI goals in the past decades. The existing CMOS technology is facing challenges related to short channel effects and reached to its performance limits at sub-10 nm technology nodes. The negative capacitance field-effect transistor is a potential device for near future technology to overcome these challenges. In the present work, negative capacitance Junctionless (NC-JL) FinFET with Metal-Ferroelectric–Insulator-Semiconductor (MFIS) structure is proposed and analysed comprehensively using TCAD simulation for its scaling capability over the various technology nodes starting from 24 nm to 5 nm. It is revealed that the integration of negative capacitance (NC) with JL FinFET helps to reduce the leakage current, short channel effects such as subthreshold slope, DIBL and provide high drive current as well as fast switching by reducing intrinsic delay for extremely short channel length as compared to standard-JL FinFET. Furthermore, the different performance parameters including Gate Induced Drain Leakage Current (GIDL) of proposed NC-JL FinFET are comprehensively studied.

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Acknowledgements

The authors would like to thank the Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur, Himachal Pradesh, India for providing valuable support to carry out this study in VLSI & Nano Laboratory.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur (NITH), Hamirpur, H.P., 177005, India

    Shelja Kaushal & Ashwani K. Rana

  2. Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology (TIET), Patiala, Punjab, 147004, India

    Rajneesh Sharma

Authors
  1. Shelja Kaushal
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  2. Ashwani K. Rana
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Contributions

Design, Methodology, Formal analysis, and investigation, Validation, Writing - original draft preparation: [Shelja Kaushal]; Conceptualization, Resources, Supervision: [Ashwani K. Rana]; Writing - review and editing: [Rajneesh Sharma].

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Correspondence to Shelja Kaushal.

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Kaushal, S., Rana, A.K. & Sharma, R. Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling. Silicon 13, 3681–3690 (2021). https://doi.org/10.1007/s12633-020-00931-2

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  • DOI: https://doi.org/10.1007/s12633-020-00931-2

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