In aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiation-hardened based design (RHBD) like twelve-transistor (12T) Dice, 12T We-Quatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and area. The 10T SRAM cell had been developed to reduce the power dissipation and area overhead. But the analysis of 10T cell shows a write failure at high-frequency. An RHBD 12T SRAM cell has been proposed in this paper. The proposed 12T SRAM cell consumes less total, and static power dissipation compared to 12T We-Quatro and 12T Dice cell, respectively. The critical charge and hold noise margin of the proposed SRAM cell have been improved compared to We-Quatro and Dice cell. The simulated result shows that the proposed SRAM cell has provided the less and comparable area, high write speed, and good writability under process variations. Finally, the Monte Carlo Simulation of SRAM cells under 45 nm CMOS technology validates the efficiency of the 12T proposed cell.

在航空航天应用中，传统的静态随机存取存储器（SRAM）面临着高度的软错误问题，例如单事件失败。为了解决软错误问题，已经开发了几种基于辐射硬化的设计（RHBD），例如十二晶体管（12T）骰子，12T We-Quatro SRAM单元等。但是它们都消耗了相对更多的总功率和静态功率，并且具有更多的延迟和面积。已开发出10T SRAM单元以减少功耗和面积开销。但是对10T单元的分析显示了高频下的写入失败。本文提出了一种RHBD 12T SRAM单元。与12T We-Quatro和12T Dice单元相比，拟议的12T SRAM单元消耗的总电量和静态功耗更低。与We-Quatro和Dice单元相比，所建议的SRAM单元的临界电荷和保持噪声容限得到了改善。仿真结果表明，所提出的SRAM单元在工艺变化的情况下具有较小且可比的面积，较高的写入速度和良好的可写性。最后，在45 nm CMOS技术下对SRAM单元进行的蒙特卡洛模拟验证了所提出的12T单元的效率。