In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to implement the ultra low power systems where the performance is not pivotal issue. Analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure have been detailed out. Impact of supply voltage, temperature and the variation of the process parameters like oxide thickness, silicon thickness, doping concentrations have been discussed in depth. Extensive simulations have been done using SILVACO ATLAS to validate analytical data of the power, delay and PDP of the proposed model for different channel length. Based on the analytical and simulated data, optimum conditions have been chosen for the proposed model. It has been observed that the proposed model can perform efficaciously in sub threshold regime without sacrificing noise immunity.

本文首次在亚阈值范围内驱动了基于无结双栅极MOSFET的高效电荷恢复逻辑（JL-ECRL）电路，以实现性能不是关键问题的超低功耗系统。亚阈值JL逆变器结构的功耗，延迟和功率延迟乘积（PDP）的分析模型已经详细列出。深入讨论了电源电压，温度的影响以及工艺参数（例如氧化物厚度，硅厚度，掺杂浓度）的变化。使用SILVACO ATLAS进行了广泛的仿真，以验证所建议模型在不同信道长度下的功率，延迟和PDP的分析数据。根据分析和模拟数据，为拟议模型选择了最佳条件。