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Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

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Abstract

In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to implement the ultra low power systems where the performance is not pivotal issue. Analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure have been detailed out. Impact of supply voltage, temperature and the variation of the process parameters like oxide thickness, silicon thickness, doping concentrations have been discussed in depth. Extensive simulations have been done using SILVACO ATLAS to validate analytical data of the power, delay and PDP of the proposed model for different channel length. Based on the analytical and simulated data, optimum conditions have been chosen for the proposed model. It has been observed that the proposed model can perform efficaciously in sub threshold regime without sacrificing noise immunity.

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References

  1. Chanda M, Jain S, De S, Sarkar CK (2015) Implementation of sub threshold adiabatic logic (SAL) for ultra low power application. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(12):2782–2790

    Article  Google Scholar 

  2. Oklobdzija EHVG, Maksimovic D, Lin FC (1997) Pass-transistor adiabatic logic using single power-clock supply. IEEE Trans Circuits Syst II Analog Digit Signal Process 44(10):842–846

    Article  Google Scholar 

  3. Chanda M, Mal S, Mondal A, Sarkar CK (2018) Design and analysis of a logic model for ultra-low power near threshold adiabatic computing. IET Circ Devices Syst 12(4):439–446

    Article  Google Scholar 

  4. Tenace V, Calimera A, Macii E, Poncino M (2016) Quasi-adiabatic logic arrays for silicon and beyond-silicon energy-efficient ICs. IEEE TCAS II 3(12):1111–1115

    Google Scholar 

  5. Chanda M, Basak J, Sinha D, Ganguli T, Chandan KS (2016) Comparative analysis of adiabatic logics in sub-threshold regime for ultra-low power application. IEEE ICEDSS, 37–41, 1988

  6. Sarkar A, De S, Chanda M, Sarkar CK (2016) Low Power VLSI Design: Fundamentals. Walter de Gruyter GmbH & Co KG

  7. Hanson S, Seok M, Sylvester D, Blaauw D (2008) Nanometer device scaling in sub-threshold logic and SRAM. IEEE Trans Electron Devices 55(1):175–185

    Article  Google Scholar 

  8. Kim J, Han J-W, Meyyappan M (2018) Reduction of variability in Junctionless and inversion-mode FinFETs by stringer gate structure. IEEE TED 65(2):470–475

    Article  CAS  Google Scholar 

  9. Lotze N, Manoli Y (2017) Ultra-sub-threshold operation of always-on digital circuits for IoT applications by use of Schmitt trigger gates. IEEE TCAS-I Regular Paper 64(11):2920–2933

    Google Scholar 

  10. Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP (2009) Junctionless multigate field-effect transistor. Appl Phys Lett 94(5):053511-1–053511-2

    Google Scholar 

  11. Chanda M, De S, Sarkar CK (2015) Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect. J Comput Electron, Springer 14(1):262–269

    Article  CAS  Google Scholar 

  12. Xie Q, Wang Z, Taur Y (2017) Analysis of Short-Channel effects in Junctionless DG MOSFETs. IEEE TED 64(8):3511–3514

    Article  CAS  Google Scholar 

  13. Doria RT, Pavanello MA, Trevisoli RD, de Souza M, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge JP (2011) Junctionless multiple-gate transistors for analog applications. IEEE Trans Electron Devices 58(8):2511–2519

    Article  CAS  Google Scholar 

  14. Parihar MS, Ghosh D, Kranti A (2013) Ultra low power Junctionless MOSFETs for subthreshold logic applications. IEEE TED 60(5):1540–1546

    Article  Google Scholar 

  15. Chiang TK (2016) A new device-physics-based noise margin/logic swing model of surrounding-gate MOSFET working on subthreshold logic gate. IEEE Trans Electron Devices 63(11):4209–4217

    Article  CAS  Google Scholar 

  16. Alioto M (2010) Understanding DC behavior of subthreshold CMOS logic through closed-form analysis. IEEE TCAS-I 57(7):1597–1607. https://doi.org/10.1109/TCSI.2009.2034233

    Article  Google Scholar 

  17. Jaiswal N, Kranti A (2018) Modeling Short-Channel effects in asymmetric Junctionless MOSFETs WithUnderlap. IEEE TED 65(9):3669–3675. https://doi.org/10.1109/TED.2018.2856839

    Article  CAS  Google Scholar 

  18. ATLAS (2015) User’s manual, Santa Clara, CA, USA

  19. Jazaeri F, Barbut L, Koukab A, Sallese J-M (2013) Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid State Electron 82:103–110,ISSN 0038-1101. https://doi.org/10.1016/j.sse.2013.02.001

    Article  CAS  Google Scholar 

  20. Enz CC, Krummenacher F, Vittoz EA (1995) An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr Circ Sig Process J Low-Voltage Low-Power Des 8:83–114. https://doi.org/10.1007/BF01239381

    Article  Google Scholar 

  21. Trivedi VP, Fossum JG (2005) Quantum–mechanical effects on the threshold voltage of undoped double-gate MOSFETs. IEEE Electron Device Lett 26(8):579–582

    Article  CAS  Google Scholar 

  22. Granzner R, Schwierz F, Polyakov V (2007) An analytical model for the threshold voltage shift caused by two-dimensional quantum confinement in undoped multiple-gate MOSFETs. IEEE Trans Electron Devices 54(9):2562–2565

    Article  CAS  Google Scholar 

  23. Moon Y, Jeong D-K (1996) An efficient charge recovery logic circuit. IEEE J Solid State Circuits 31(4):514–522

    Article  Google Scholar 

  24. Aldegunde M, Martinez A, Barker JR (2012) Study of discrete doping-induced variability in Junctionless nanowire MOSFETs using dissipative quantum transport simulations. IEEE EDL 33(2):194–196. https://doi.org/10.1109/LED.2011.2177634

    Article  CAS  Google Scholar 

  25. Gnudi A, Reggiani S, Gnani E, Baccarani G (2012) Analysis of threshold voltage variability due to random dopant fluctuations in Junctionless FETs. IEEE Electron Device Lett 33(3):336–338. https://doi.org/10.1109/LED.2011.2181153

    Article  Google Scholar 

  26. Pravin JC, Nirmal D, Prajoon P, Menokey MA (2016) A new drain current model for a dual metal Junctionless transistor for enhanced digital circuit performance. IEEE Trans Electron Devices 63(9):3782–3789

    Article  Google Scholar 

  27. Leung G, Chui CO (2012) Variability impact of random dopant fluctuation on Nanoscale Junctionless FinFETs. IEEE Electron Device Lett 33(6):767–769. https://doi.org/10.1109/LED.2012.2191931

    Article  Google Scholar 

  28. Pravin JC, Nirmal D, Prajoon P, Ajayan J (2016) Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications. Phys E: Low-Dimens Syst Nanostruct 83:95–100

    Article  Google Scholar 

  29. Padmanaban B, Ramesh R, Nirmal D, Sathiyamoorthy S (2015) Numerical modeling of triple material gate stack gate all-around (TMGSGAA) MOSFET considering quantum mechanical effects. Superlattice Microst 82:40–54

    Article  CAS  Google Scholar 

  30. Mizuno T, Okumtura J, Toriumi A (1994) Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's. IEEE Trans Electron Devices 41(11):2216–2221. https://doi.org/10.1109/16.333844

    Article  CAS  Google Scholar 

  31. Das R, Chanda M, Sarkar CK (2018) Analytical modeling of charge plasma-based optimized nanogap embedded surrounding gate MOSFET for label-free biosensing. IEEE Trans Electron Devices 65(12):5487–5493

    Article  CAS  Google Scholar 

  32. Bhattacharyya A, Chanda M, De D (2020) GaAs0. 5Sb0. 5/In0. 53Ga0. 47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement. Superlattice Microst, Elsevier 142:106522

    Article  CAS  Google Scholar 

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Acknowledgments

Author would like to thank Advanced VLSI Lab, Meghnad Saha Institute of Technology, ECE Department, Kolkata, to use their re-sources and support.

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Correspondence to Swarnil Roy.

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Roy, S., Jana, G. & Chanda, M. Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application. Silicon 14, 903–911 (2022). https://doi.org/10.1007/s12633-020-00870-y

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