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Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling
Silicon ( IF 2.8 ) Pub Date : 2021-01-05 , DOI: 10.1007/s12633-020-00879-3
Prashanth Kumar , Adla Vinod , Krishna Dharavath , Brinda Bhowmick

A novel analytical model of surface potential for a double metal gate schottky barrier tunnelling (SBT) FET using schottky tunnelling with HfO2 as gate dielectric is proposed. The presence of a schottky tunnelling at source-channel interface improves the drain current because of the advanced tunneling from one band-to- another band charge carriers in the area of the interface junctions. Moreover, the existence of the duel work-function- improved the conductivity and thus enhances the tunnelling probability, which increases device performance. The surface potential along the channel the model is examined using the two-dimensional (2-D) Poisson equation with suitable boundary conditions and shows a major part in the design of the shortest distance between source/channel and the drain-source current. Due to its high tunnelling increases on-state current, expressively reduced off-sate current, the proposed device represents one of the reliable model to substitute complementary metal-oxide-semiconductor (CMOS) technology. The results of the analytical model are confirmed against those attained using the silvaco device simulator.



中文翻译:

肖特基势垒场效应管的二维分析建模与仿真

使用HfO 2的肖特基隧道效应的双金属栅肖特基势垒隧穿(SBT)FET的表面势的新型分析模型作为栅极电介质被提出。源极-沟道界面处的肖特基隧穿的存在改善了漏极电流,因为在界面结的区域中从一个带到另一个带电荷载流子进行了高级隧穿。此外,对决功函数的存在提高了导电性,从而提高了隧穿概率,从而提高了器件性能。使用具有适当边界条件的二维(2-D)泊松方程检查了模型沿通道的表面电势,并显示了设计中源/通道与漏-源电流之间最短距离的主要部分。由于其较高的隧道效应,增加了通态电流,显着降低了桥外电流,拟议的设备代表了一种可靠的模型来替代互补金属氧化物半导体(CMOS)技术。与使用silvaco设备模拟器获得的结果相比,可以确认分析模型的结果。

更新日期:2021-01-06
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