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Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling

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Abstract

A novel analytical model of surface potential for a double metal gate schottky barrier tunnelling (SBT) FET using schottky tunnelling with HfO2 as gate dielectric is proposed. The presence of a schottky tunnelling at source-channel interface improves the drain current because of the advanced tunneling from one band-to- another band charge carriers in the area of the interface junctions. Moreover, the existence of the duel work-function- improved the conductivity and thus enhances the tunnelling probability, which increases device performance. The surface potential along the channel the model is examined using the two-dimensional (2-D) Poisson equation with suitable boundary conditions and shows a major part in the design of the shortest distance between source/channel and the drain-source current. Due to its high tunnelling increases on-state current, expressively reduced off-sate current, the proposed device represents one of the reliable model to substitute complementary metal-oxide-semiconductor (CMOS) technology. The results of the analytical model are confirmed against those attained using the silvaco device simulator.

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Authors and Affiliations

  1. School of Electronics Engineering, Vellore Institute of Technology (VIT), Chennai, India

    Prashanth Kumar

  2. Department of Electrical and Electronics Engineering, Marri Laxman Reddy Institute of Technology and Management Dundigal, Hyderabad, Telangana, 500 043, India

    Adla Vinod

  3. Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad, Telangana, 501218, India

    Krishna Dharavath

  4. Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam, 788010, India

    Brinda Bhowmick

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  1. Prashanth Kumar
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  2. Adla Vinod
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  3. Krishna Dharavath
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  4. Brinda Bhowmick
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Contributions

All the authors are involved in review on the schottky barrier FET and Simulation and modeling of the device.

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Correspondence to Prashanth Kumar.

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Kumar, P., Vinod, A., Dharavath, K. et al. Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling. Silicon 14, 831–837 (2022). https://doi.org/10.1007/s12633-020-00879-3

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  • DOI: https://doi.org/10.1007/s12633-020-00879-3

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