This paper describes the design of an optimal and low power Digital Phase Lock Loop (DPLL). It consumes the 485 mV power using 45 nm CMOS technology on CADENCE Virtuoso software. DPLL used for fast speed, less noise or jitter and large bandwidth with very fast acquisition time in wireless or wire line communication for modulator or demodulator. Clock recover, clock synchronization are the important factor in which PLL used. In digital system and microprocessor the DPLL uses for the clock generation and frequency synthesizer. DPLL consist the phase detector, low pass filter and VCO. The VCO produced oscillations at 8.5 Ghz. The average power dissipation or power consumption of DPLL is 485mV at an input voltage of 2 V. The results show that of the proposed DPLL design used for less power consumption, high speed operations applications.

本文介绍了一种最佳的低功耗数字锁相环（DPLL）的设计。它使用CADENCE Virtuoso软件上的45 nm CMOS技术消耗485 mV功率。DPLL用于在调制器或解调器的无线或有线通信中具有非常快的采集时间的快速度，较低的噪声或抖动以及较大的带宽。时钟恢复，时钟同步是使用PLL的重要因素。在数字系统和微处理器中，DPLL用于时钟生成和频率合成器。DPLL由鉴相器，低通滤波器和VCO组成。VCO在8.5 Ghz处产生振荡。在2 V的输入电压下，DPLL的平均功耗为485mV。结果表明，所建议的DPLL设计用于更低的功耗，高速操作应用。