In this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285.77 \(\upmu\) w. The design is based on standard 0.18 \(\upmu\) m CMOS process technology with the supply voltage of 1.8 V and achieves phase noise of \(-135.45\) dBc/Hz at 1 MHz offset. Further, the proposed design has minimized the Blind zone to 63 ps and has completely eliminated the dead zone in the phase characteristics. This is required for low noise phase locked loop (PLL) application.

在本文中，提出并分析了基于CMOS的预充电相位频率检测器（PPFD），该检测器具有改进的锁相环（PLL）输出特性。提出的PFD可以最大程度地缩短复位时间，以改善输出特性，并能在1.25 MHz至3.8 GHz的频率下工作。此外，它还具有预充电PFD的优势，它具有低功耗能力，即285.77  \（\ upmu \）  w。该设计基于标准的0.18 \（\ upmu \）  m CMOS工艺技术，电源电压为1.8 V，并实现了\（-135.45 \）的相位噪声。 1 MHz偏移时的dBc / Hz。此外，提出的设计将盲区最小化到63 ps，并完全消除了相位特性中的死区。这是低噪声锁相环（PLL）应用所必需的。