In this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence virtuoso tool under 45 nm CMOS technology. Supply voltage is + 0.5 V.

中文翻译：

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用于DSP应用的高能效近似加法器

本文针对DSP处理器提出了近似加法器。DSP处理器主要由底层的加法器和乘法器组成。在晶体管级设计中将功耗降至最低。与现有的近似加法器相比，建议的加法器具有更低的功耗。结果表明，所提出的加法器具有更少的PDP和更高的精度。电路在Cadence virtuoso工具中以45 nm CMOS技术进行了仿真。电源电压为+ 0.5V。