We report the effect of bias stress on the drain current and threshold voltage of n-channel thin-film transistors based on solution processed In₂O₃ layers. Application of a positive gate bias for variable time-periods led to displacements of the transfer curves in the positive gate bias direction. On switching off the gate bias, the transfer curves returned close to their pre-stress state on a timescale similar to that when the gate bias was switched on. The time dependence of the threshold voltage shift is described well by a stretched-exponential model. The temporal behaviour of the threshold voltage shifts is consistent with charge trapping as the dominant effect, although some defect formation cannot be ruled out.

我们基于在₂ O ₃层中处理的溶液，报告了偏应力对n沟道薄膜晶体管的漏极电流和阈值电压的影响。在可变时间段内施加正栅极偏置会导致传输曲线在正栅极偏置方向上发生位移。关断栅极偏置时，传输曲线在类似于栅极偏置打开时的时间尺度上返回接近其预应力状态。阈值电压偏移的时间依赖性可以通过拉伸指数模型很好地描述。尽管不能排除某些缺陷的形成，但阈值电压偏移的时间行为与电荷俘获为主导效应相一致。