This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p-doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn-doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p-doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current–voltage and capacitance–voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 10¹² cm⁻² related to the Al₂O₃ gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.

本文演示了第一个基于氮化镓（GaN）鳍结构并具有反向p掺杂沟道层的垂直场效应晶体管。采用自上而下的混合蚀刻方法，将感应耦合等离子体反应离子蚀刻和基于KOH的湿法蚀刻相结合，以制造具有光滑a面侧壁的GaN鳍的规则场。使用腔体逐步流动模型解释获得的形态。已经开发了3D处理方案，并通过聚焦离子束横截面进行了评估。自上而下的方法允许沿沟道引入任意掺杂轮廓而不会长生，从而能够调制沟道特性，从而增加了器件概念的灵活性。在这里，垂直NPN掺杂分布被用来实现常关操作以增加的阈值电压高达2.65伏。p掺杂区和环绕侧壁的3D栅极在电介质和半导体之间的界面附近创建了非常狭窄的垂直电子通道，从而实现了良好的静电栅极控制，通过内部鳍片芯的低泄漏电流以及对GaN之间的界面的高灵敏度和栅极氧化物。进行了流体动力传输模拟，并与执行的电流-电压和电容-电压测量显示出良好的一致性。模拟表明通道迁移率降低，这归因于界面散射在窄通道中特别重要。我们还证明了氧化物和界面陷阱的存在，其与Al ₂ O ₃有关的估计薄片密度为3.2 10 ¹² cm ^-2。栅极电介质导致亚阈值摆幅增加。因此，提高接口质量对于充分发挥所提出的垂直3D晶体管概念的潜力至关重要。