High temperature during test mode and the large volume of test data are the two prominent challenges in the testing of System-on-Chip (SoC). Temperature relies on the spatial power distribution between the blocks of the chip. An efficient don’t care filling technique is proposed to minimize the non-uniform spatial power distribution, which, in turn, reduces the peak temperature of the chip. However, high test data compression can be obtained by carefully mapping the don’t care bits to get more similar subvectors in the precomputed test patterns. The don’t care bits in the given test set can be utilized for test data compression and peak temperature reduction. As the same don’t care bits are to be used for both peak temperature reduction and test data compression, the two techniques conflict with each other. An integrated approach is presented to keep peak temperature under the safe limit with low test compression loss. Experimental results on ISCAS’89 benchmark circuits demonstrate the effectiveness of the proposed approach

中文翻译：

---

基于改进位掩码方法的片上系统热感知测试数据压缩

测试模式期间的高温和大量测试数据是片上系统 (SoC) 测试中的两个突出挑战。温度取决于芯片块之间的空间功率分布。提出了一种有效的不关心填充技术来最小化非均匀空间功率分布，从而降低芯片的峰值温度。然而，通过仔细映射无关位以获得预计算的测试模式中更相似的子向量，可以获得高测试数据压缩。给定测试集中的无关位可用于测试数据压缩和峰值温度降低。由于峰值温度降低和测试数据压缩都使用相同的无关位，因此这两种技术相互冲突。提出了一种综合方法，以将峰值温度保持在安全极限以下，同时测试压缩损失较低。ISCAS'89 基准电路的实验结果证明了所提出方法的有效性