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Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods

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Abstract

High temperature during test mode and the large volume of test data are the two prominent challenges in the testing of System-on-Chip (SoC). Temperature relies on the spatial power distribution between the blocks of the chip. An efficient don’t care filling technique is proposed to minimize the non-uniform spatial power distribution, which, in turn, reduces the peak temperature of the chip. However, high test data compression can be obtained by carefully mapping the don’t care bits to get more similar subvectors in the precomputed test patterns. The don’t care bits in the given test set can be utilized for test data compression and peak temperature reduction. As the same don’t care bits are to be used for both peak temperature reduction and test data compression, the two techniques conflict with each other. An integrated approach is presented to keep peak temperature under the safe limit with low test compression loss. Experimental results on ISCAS’89 benchmark circuits demonstrate the effectiveness of the proposed approach

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Authors and Affiliations

  1. Department of ECE, Kongu Engineering College, Perundurai, TamilNadu, India

    Azhaganantham Arulmurugan, Govindasamy Murugesan & Balasubramaniam Vivek

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  1. Azhaganantham Arulmurugan
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  2. Govindasamy Murugesan
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  3. Balasubramaniam Vivek
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Correspondence to Azhaganantham Arulmurugan.

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Arulmurugan, A., Murugesan, G. & Vivek, B. Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods. J Electron Test 36, 577–590 (2020). https://doi.org/10.1007/s10836-020-05902-4

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  • DOI: https://doi.org/10.1007/s10836-020-05902-4

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