Implementation of efficient power distribution network is a challenging task in modern day system-on-chip. During switching of transistors the signal integrity problems arises, such as, resistive drop, inductive noise and electro-migration, causing voltage fluctuations known as supply noise. This supply noise may result in malfunctioning of the integrated circuit. Insertion of decoupling capacitance is a commonly used technique for suppression of supply noise. In this article flower pollination algorithm has been used to estimate the decoupling capacitor budget to reduce power supply noise. Another major issue is allocation of decoupling capacitors in the floorplan of the design. To get the best possible results in the post-layout stage particle swarm optimization algorithm has been used in the floorplan stage. The purpose of this work is to reduce the supply noise without having much effect on the other design parameters of the chip. Simulation results show that noise voltage has been reduced significantly without much effecting other design parameters. This approach can be used in any system-on-chip.

在现代片上系统中，高效配电网络的实施是一项艰巨的任务。在晶体管切换期间，出现信号完整性问题，例如电阻降，电感噪声和电迁移，从而引起称为电源噪声的电压波动。这种电源噪声可能导致集成电路故障。插入去耦电容是抑制电源噪声的常用技术。在本文中，花授粉算法已被用来估计去耦电容器的预算，以减少电源噪声。另一个主要问题是在设计布局图中分配去耦电容器。为了在布局后阶段获得最佳结果，在平面布置阶段使用了粒子群优化算法。这项工作的目的是在不影响芯片其他设计参数的情况下降低电源噪声。仿真结果表明，噪声电压已大大降低，而对其他设计参数没有太大影响。这种方法可以在任何片上系统中使用。