Abstract
Implementation of efficient power distribution network is a challenging task in modern day system-on-chip. During switching of transistors the signal integrity problems arises, such as, resistive drop, inductive noise and electro-migration, causing voltage fluctuations known as supply noise. This supply noise may result in malfunctioning of the integrated circuit. Insertion of decoupling capacitance is a commonly used technique for suppression of supply noise. In this article flower pollination algorithm has been used to estimate the decoupling capacitor budget to reduce power supply noise. Another major issue is allocation of decoupling capacitors in the floorplan of the design. To get the best possible results in the post-layout stage particle swarm optimization algorithm has been used in the floorplan stage. The purpose of this work is to reduce the supply noise without having much effect on the other design parameters of the chip. Simulation results show that noise voltage has been reduced significantly without much effecting other design parameters. This approach can be used in any system-on-chip.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Chen S, Luk BL (2010) Digital IIR filter design using particle swarm optimization. Int J Model Identif Control Indersci 9(4):327–335
Das D (2005) VLSI design, 2nd edn. Oxford University Press, New Delhi
De BP, Kar R, Mandal D, Ghosal SP (2015) Particle swarm optimization with ageing leader and challengers for optimal Design of Analog Active Filters. Circ Syst Signal Process, Springer 34:707–737
Gudise VG, Venayagamoorthy GK (2004) FPGA placement and routing using particle swarm optimization. Proc IEEE Comput Soc Ann Symp VLSI, pp. 307-308
Karim T (2012) ‘On-Chip power supply noise: scaling, suppression and detection. Dissertation, doctor of philosophy (electrical and computer engineering)’, University of Waterloo
Mitra P, Bhaumik J (2019) A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stage. Microsyst Technol, Springer 25(5):1977–1986
Pant S (2008) Design and analysis of power distribution networks in VLSI circuits. Dissertation, doctor of philosophy (electrical engineering), University of Michigan
Shah K (2007) Power grid analysis in VLSI designs. Dissertation, master of science (engineering). Super computer education and research Centre, Indian Institute of Science, Bangalore
Yang XS(2012) Flower pollination algorithm for global optimization. LNCS 7445, Springer, pp.240–249
Zhao S, Roy K, Koh CK (2002) Decoupling capacitance allocation and its application to power-supply noise-aware flooring. IEEE Trans Comput Aided Des Integr Circ Syst 21(1):81–92
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: V. D. Agrawal
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Mitra, P., Sarkar, A. Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip. J Electron Test 36, 665–669 (2020). https://doi.org/10.1007/s10836-020-05903-3
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-020-05903-3