This paper presents the design and implementation of a low complexity and highly efficient configurable singular value decomposition (SVD) processor for 2 × 2, 4 × 4, 6 × 6, and 8 × 8 MIMO wireless communication systems. In order to minimize the area complexity while maintaining comparable throughput, novel data-processing sequences are proposed so that costly matrix multipliers are eliminated. Furthermore, data dependencies are greatly mitigated due to the proposed processing sequences. Therefore, a highly optimized pipelined architecture is designed where the resource utilization and hardware efficiency are significantly improved. Moreover, circuit level optimizations are also applied to further enhance the performance of the proposed SVD processor. The proposed SVD architecture has been implemented with 90 nm technology at 500 MHz clock frequency. The post-layout estimations show that the proposed SVD processor achieves a throughput of 1.1 M matrices/s for 8 × 8 MIMO communication systems with the hardware complexity of 192.2 kilo Gate Equivalents. Compared to the state-of-the-art design that supports 2 × 2, 4 × 4, 6 × 6, and 8 × 8 MIMO configurations, the proposed architecture demonstrates a 46% reduction in area complexity and a 22% improvement in hardware efficiency.

中文翻译：

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用于 MIMO 通信系统的低复杂度和高效可配置 SVD 处理器的 VLSI 架构和实现

本文介绍了用于 2 × 2、4 × 4、6 × 6 和 8 × 8 MIMO 无线通信系统的低复杂度和高效的可配置奇异值分解 (SVD) 处理器的设计和实现。为了在保持可比吞吐量的同时最小化区域复杂性，提出了新的数据处理序列，从而消除了昂贵的矩阵乘法器。此外，由于建议的处理序列，大大减轻了数据依赖性。因此，设计了高度优化的流水线架构，显着提高了资源利用率和硬件效率。此外，还应用了电路级优化以进一步提高所提出的 SVD 处理器的性能。建议的 SVD 架构已在 500 MHz 时钟频率下使用 90 nm 技术实现。布局后估计表明，对于硬件复杂度为 192.2 千门等效值的 8 × 8 MIMO 通信系统，所提出的 SVD 处理器实现了 1.1 M 矩阵/秒的吞吐量。与支持 2 × 2、4 × 4、6 × 6 和 8 × 8 MIMO 配置的最新设计相比，所提出的架构展示了面积复杂度降低 46% 和硬件改进 22%效率。