p-Si/4H-SiC heterojunction diodes are realized by sputter-deposition of the Si top contact and subsequent post-deposition annealing at either 900 °C or 1000 °C. The high Schottky barrier height (SBH) of this junction architecture of around 1.65 V is ideal to analyze SBH inhomogeneities present in most Schottky- and heterojunctions. Current-voltage-temperature (IVT) and capacitance-voltage-temperature (CVT) measurements are conducted in a wide temperature range from 60 K up to 460 K while applying standard techniques for SBH extraction. Strong deviations from ideal IV characteristics are present especially at lowest temperatures when assuming a homogenous SBH. Additionally, the extracted SBHs at low temperatures differ a lot between the two methods, indicating the presence of low barrier conduction paths. The presence of at least two distinct SBH inhomogeneities is found, which are labeled as ‘intrinsic’ and ‘extrinsic’. Next, the Tung model was applied to fit the measured IVT da...

中文翻译：

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多晶硅Si / 4H-SiC异质结二极管中势垒高度不均匀性的理论和实验研究

p-Si / 4H-SiC异质结二极管是通过Si顶部触点的溅射沉积以及随后在900°C或1000°C下的后沉积退火实现的。这种结结构的高肖特基势垒高度（SBH）约为1.65 V，是分析大多数肖特基和异质结中存在的SBH不均匀性的理想选择。电流-电压-温度（IVT）和电容-电压-温度（CVT）测量在60 K至460 K的宽温度范围内进行，同时应用了用于SBH提取的标准技术。假设均质SBH，尤其是在最低温度下，会出现与理想IV特性的强烈偏差。此外，两种方法之间在低温下提取的SBH之间存在很大差异，表明存在低势垒传导路径。发现存在至少两种不同的SBH不均匀性，分别标记为“本征”和“本征”。接下来，应用Tung模型以拟合测得的IVT数据。