Abstract

The junctionless MOS-transistors (junctionless MOSFET) have a number of advantages over conventional transistors in terms of the simplicity of design, manufacturing technology, and reduction of the impact of short-channel effects on the characteristics of the device. However, the well known experimental nanowire junctionless MOSFET have high subthreshold currents due to the appearance of the parasitic bipolar transistor effect in a closed state. The structural model of a planar SOI junctionless MOSFET by the technology standards of 90 nm and the route of mathematical simulation using the Synopsys Sentaurus TCAD environment are developed. The influence of the impurity concentration in a SOI silicon film of a junctionless MOSFET at the threshold voltage, saturation currents, and subthreshold currents is investigated. The research results reveal that at the impurity concentrations in the working channel of the device below 10¹⁷ cm^–3, when the effect of band-to-band tunneling is absent and the parasitic bipolar transistor effect does not arise, the subthreshold currents decrease up to 10^–13 A/μm, which is significantly lower than those of the conventional MOSFET, while maintaining the saturation currents at an acceptable level.

中文翻译：

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具有低亚阈值电流的无结MOS晶体管

摘要

就设计的简单性，制造技术以及减少短沟道效应对器件特性的影响而言，无结MOS晶体管（无结MOSFET）与常规晶体管相比具有许多优势。但是，由于在闭合状态下出现了寄生双极晶体管效应，因此众所周知的实验性纳米线无结MOSFET具有较高的亚阈值电流。根据Synopsys Sentaurus TCAD环境，开发了基于90 nm技术标准的平面SOI无结MOSFET的结构模型和数学仿真路线。研究了在阈值电压，饱和电流和亚阈值电流下，无结MOSFET的SOI硅膜中杂质浓度的影响。¹⁷ cm ^–3，当不存在带间隧穿效应且没有出现寄生双极晶体管效应时，亚阈值电流降低至10 ^–13 A /μm，这明显低于常规MOSFET的电流。，同时将饱和电流保持在可接受的水平。