Junctionless MOS-Transistor with a Low Subthreshold Current

Abstract

The junctionless MOS-transistors (junctionless MOSFET) have a number of advantages over conventional transistors in terms of the simplicity of design, manufacturing technology, and reduction of the impact of short-channel effects on the characteristics of the device. However, the well known experimental nanowire junctionless MOSFET have high subthreshold currents due to the appearance of the parasitic bipolar transistor effect in a closed state. The structural model of a planar SOI junctionless MOSFET by the technology standards of 90 nm and the route of mathematical simulation using the Synopsys Sentaurus TCAD environment are developed. The influence of the impurity concentration in a SOI silicon film of a junctionless MOSFET at the threshold voltage, saturation currents, and subthreshold currents is investigated. The research results reveal that at the impurity concentrations in the working channel of the device below 10¹⁷ cm^–3, when the effect of band-to-band tunneling is absent and the parasitic bipolar transistor effect does not arise, the subthreshold currents decrease up to 10^–13 A/μm, which is significantly lower than those of the conventional MOSFET, while maintaining the saturation currents at an acceptable level.