The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

中文翻译：

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RISC 处理器的基于高级实现独立功能软件的自检

本文提出了一种新的高级方法，用于为具有 RISC 架构的处理器生成与实现无关的基于功能软件的自测程序。该方法可以快速生成具有高固定故障覆盖率的制造测试。该方法的主要概念是基于对高级功能单元的控制和数据部分的单独测试生成。对于控制部分，引入了一种新颖的高级控制故障模型，而对于数据部分，可以应用伪穷举测试方法来保持与实现细节的独立性。对于控制部分，提出了一种新的高级故障模拟方法来评估高级故障覆盖率。该方法可用于轻松识别控制部分中的冗余门级故障。当实施可用时，可以通过生成的高级测试的简单门级故障模拟来识别冗余故障。RISC 处理器不同单元的测试生成实验结果支持本文提出的解决方案。