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High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

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Abstract

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

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Acknowledgements

The work has been supported by EU’s H2020 project RESCUE, Estonian research grant IUT 19-1, and funded by Excellence Centre EXCITE in Estonia.

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Correspondence to Adeboye Stephen Oyeniran.

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Appendices

Appendix A: Theoretical Foundation of The Proposed High-level Control Fault Model

Consider a set F = {fi} of functions, selected as a group of functions to be tested using the fault model of constraints (4) and (5).

Table 9 Examples of relations between 0-domains

Let us define for each function a set of patterns

$$D^{0}\left\{f_{i/k}\right\}=\left\{d | f_{i/k}(d)=0\right\}$$

for which the function fi produces the value yi/k = 0 in the bit k. Let us call the set of patterns D0 (fi/k) as the 0-domain of the function fi for the bit k.

Theorem 1

If for two functions fi/k and fj/k the following D0 {fi/k} − D0 {fj/k} = ∅ is valid, then the fault ri,j/k is functionally redundant.

Proof

From D0 {fi/k} − D0 {fj/k} = ∅ it follows that D0 {fi/k} ⊂ D0 {fj/k}. This means that for each data pattern dD0 (fi/k), we have yi/k (d) = 0, but also yj/k (d) = 0. Hence, there exists no data which can satisfy the constraint (5), and the functional fault ri,j/k according to Definition 2 is not testable, and is functionally redundant. □

From Theorem 1, the following corollaries straightforwardly result.

Corollary 1

If D0 {fi/k} − D0 {fj/k} = ∅then the difference D0 {fi/k} = D0 {fj/k} is the set of data patterns which can be used for testing the fault ri,j/k.

Corollary 2

If for all bits k, \(D^{0}\left (f_{i / k}\right )-\bigcup _{{j,j\neq i }}D^{0}\left (f_{j / k}\right ) \neq \varnothing \) is valid, then the function fi/k has unique patterns, which produce yi/k = 0 for only the function fi/k and for no one else fj/k, fjF. Each of these patterns serves as test data for detecting the faults ri,j/k for all fjF, ji.

Corollary 3

If for all bits kD0 {fi/k} − D0 {fj/k} = ∅ is valid, then the function fi is fully distinguishable from the function fj in accordance with the constraints (5), and the functional faults ri,j/k are testable for all bits of k. If all functions fjF are mutually distinguishable then the set all high-level control faults in M (F) are testable.

In Example 3, we will demonstrate the testability of selected ALU functions in a microprocessor using the proposed high-level control fault model.

Example 3

Consider, as an example, a set of three 1-bit functions f1(OR), f2(AND), and f3(XOR). The truth table of these functions fi and the Venn diagrams of the sets D0 {fi} are illustrated in Fig. 13. According to Venn diagrams, we can notice that there exist the following domains D0 (fi): D0 (OR) = {00}, D0 (AND) = {00, 01, 10}, D0 (XOR) = {00, 11}.

Fig. 13
figure 13

Three functions selected for testing as MUT

Few examples which illustrate the testability of functions OR, AND, XOR according to Corollaries 1-3, are depicted in Table 1.

Appendix B: Theoretical Foundations for Identification of Not-detectable Low-level Faults in Control Circuits

In the following we provide the main statements and proofs, which justify the identification of the not-detectable (functionally redundant) low-level faults in the real implementation of the given control circuit by its low-level fault simulation using the test T(F) constructed in Section 5.

Theorem 2

The test T (F), which covers all non-redundant high-level faults of the fault model M{F}, covers also all gate-level testable SAF in the control part of the microprocessor, which controls the set of functions F.

Proof

Consider the control part of a MUT presented at high-level in Fig. 3, and described in the real implemented version expanded as the following EDNF as explained in [1], and also in Section 3::

$$ \begin{array}{@{}rcl@{}} y&=&c_{1,1} c_{1,2} {\ldots} c_{1, p} y_{1} \vee c_{2,1} c_{2,2} {\dots} c_{2, p} y_{2} \vee {\ldots} \vee c_{n, 1} c_{n, 2}\\ &&{\dots} c_{n, p} y_{n} \end{array} $$
(6)

Here, the high-level control states siS used in the formula (1) are mapped into the control signals ci,1ci,2ci,p of the decoder of the operation code embedded in the instruction of the processor. In [1] and Section 3, it was shown that if all non-redundant appearances of the literals in the EDNF will be tested, then all the non-redundant faults in the original circuit implementation will also be tested. Let us show now, that the high-level test generated for the high-level expression (1) will also test all non-redundant faults in the expression (6).

In the EDNF (6), the variables ci,j for selecting the data results yi,i = 1,…n, represent the global control signals ci,j = 1,…p, which may be either inverted or not, and which cover, in general case, exhaustively all 2p combinations. In the EDNF, due to satisfied constraints (5) of the fault model in Definition 1, when testing the function yi , at least once the value of yj for each ij will be yj = 1. On the other hand, due to the exhaustiveness of all 2p combinations of control signals, for each term of EDNF with yi = 1, there will be a combination of control signals ci,1ci,2ci,p consisting of a single 0, e.g. ci,p = 0, with all others ci,r = 1,rp. This is the case, where in the term ci,1ci,2...ci,pyi, the SAF ci,p ≡ 1 is tested. For propagating the fault ci,p ≡ 1 to the output y, all other terms in DNF must have at least one 0 assigned to the variables of the term. This is guaranteed, because due to the constraints (5), which demand that in the term where all cj,k = 1, the value of yj must be 0, and in other terms there must be at least one variable assigned by 0. Hence, all SAF faults of type ci,p ≡ 1 in all variables ci,p can be tested by T (F). The faults ci,p ≡ 0 are tested by test data used in T (F) where the constraint (1) is satisfied. \(\blacksquare \)

Corollary 4

Any gate-level SAF in the control part related to F = {fi}, not detectable by the test T (F) which covers all not redundant high-level control faults of the model M{F}, is redundant.

Proof

In Theorem 2, exhaustiveness of using all the combinations of the local control signals ci,1ci,2ci,p was assumed. If not all combinations are used in the instruction set of the microprocessor, which is the typical practical case, then, not all patterns can be generated for activating all SAF of type ci,p ≡ 1. Usually these cases are used for optimization of the gate-level structure of the control part of ALU. If however the optimization process has not removed all hardware redundancy, then as the result, the control part may consequently contain also redundant faults. These redundant faults can be identified by simple and fast gate-level fault simulation of the high-level generated test T. □

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Oyeniran, A.S., Ubar, R., Jenihhin, M. et al. High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J Electron Test 36, 87–103 (2020). https://doi.org/10.1007/s10836-020-05856-7

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