Abstract
The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.
References
Armstrong DB (1966) On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets. IEEE Trans Electr Comput EC-15(1):66–73
Bernardi P et al (2014) On the in-field functional testing of decode units in pipelined RISC processors. Proceedings of 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, pp 299–304
Bernardi P, Ciganda L, Grosso M, Sanchez E, Sonza Reorda M (2012) A SBST strategy to test microprocessors’ Branch Target Buffer. Proceedings of 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp 306–311
Bernardi P, Cantoro R, Ciganda L, Du B, Sanchez E, Reorda MS, Grosso M, Ballan O (2013) On the functional test of the register forwarding and pipeline interlocking unit in pipelined processors. Proceedings of 14th International Workshop on Microprocessor Test and Verification, pp 52–57
Blanton RD, Hayes JP (2003) On the properties of the input pattern fault model. ACM Trans Des Autom Electron Syst 8(1):108–124
Bushnell M, Agrawal V (2013) Essentials of electronic testing for digital, memory and Mixed-Signal VLSI circuits. Springer, Berlin, p 690
Corno F, Cumani G, Sonza Reorda M, Squillero G (2000) An RT-level fault model with high gate level correlation. Proceedings of IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786), Berkeley, pp 3–8
Corno F, Sanchez E, Reorda MS, Squillero G (2004) Automatic test program generation: a case study. IEEE Des Test Comput 21(2):102–109
Cho CH, Armstrong JR (1994) B-algorithm: a behavioral test generation algorithm. Proceedings of International Test Conference, Washington, pp 968–979
Cho KY, Mitra S, McCluskey EJ (2005) Gate exhaustive testing. Proceedings of IEEE International Conference on Test, Austin, pp 7–777
Dwarakanath KN, Blanton RD (2000) Universal fault simulation using fault tuples. Proceedings of 37th Design Automation Conference, Los Angeles, pp 786–789
Georgiou P, Kavousianos X, Cantoro R, Reorda MS (2018) Fault-Independent Test-Generation For Software-Based Self-Testing. Proceedings of 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Platja d’Aro, pp 79–84
Gizopoulos D et al (2008) Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(11):1441–1453
Hapke F, Redemund W, Glowatz A, Rajski J, Reese M, Hustava M, Keim M, Schloeffel J, Fast A (2014) Cell-Aware Test. IEEE Trans Comput-Aided Des Integr Circ Syst 33(9):1396–1409
Holst S, Wunderlich H (2007) Adaptive debug and diagnosis without fault dictionaries. Proceedings of 12th IEEE European Test Symposium (ETS’07), Freiburg, pp 7–12
Jas A, Natarajan S, Patil S (2007) The Region-Exhaustive fault model. Proceedings of 16th Asian Test Symposium (ATS 2007), Beijing, pp 13–18
Keller KB (1994) Hierarchical Pattern Faults for Describing Logic Circuit Failure Mechanisms. US Patent 5546408
Kranitis N, Paschalis A, Gizopoulos D, Xenoulis G (2005) Software-based self-testing of embedded processors. IEEE Trans Comput 54(4):461–475
Kristic A, Cheng KT (1998) Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers, Dordrecht
Kumar V, et al. (2012) Employing functional analysis to study fault models in VHDL. Int J Sci Eng Technol 1(5):2017–208
Lee HK, Ha DS (1990) SOPRANO: An efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits. Proceedings of 27th ACM/IEEE Design Automation Conference, Orlando, pp 660–666
Li Z, Lu X, Qiu W, Shi W, Walker DMH (2003) A circuit level fault model for resistive opens and bridges. Proceedings of 21st VLSI Test Symposium, Napa, pp 379–384
Mahlstedt U, Alt J, Hollenbeck I (1995) Deterministic test generation for non-classical faults on the gate level. Proceedings of Fourth Asian Test Symposium, Bangalore, pp 244–251
OpenCores, “MiniMIPS ISA”
Oyeniran AS, Ubar R, Azad SP, Raik J (2017) High-level test generation for processing elements in many-core systems. Proceedings of 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Madrid, pp 1–8
Oyeniran AS, Azad SP, Ubar R (2018) Parallel Pseudo-Exhaustive testing of array multipliers with Data-Controlled segmentation. Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, pp 1–5
Oyeniran AS, Ubar R, Jenihhin M, Gürsoy CC, Raik J (2019) Mixed-level identification of fault redundancy in microprocessors. Proceedings of 2019 IEEE Latin American Test Symposium (LATS), Santiago, pp 1–6
Oyeniran AS, Ubar R, Jenihhin M, Gürsoy CC, Raik J (2019) High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. 2019 IEEE European Test Symposium (ETS), Baden-Baden, pp 1–6
Psarakis M, Gizopoulos D, Paschalis A, Zorian Y (2000) Sequential fault modeling and test pattern generation for CMOS iterative logic arrays. IEEE Trans Comput 49(10):1083–1099
Raik J, Ubar R, Sudbrock J, Kuzmicz W, Pleskacz W (2005) DOT: New deterministic defect-oriented ATPG tool. Proceedings of European Test Symposium (ETS’05), Tallinn, pp 96–101
Riefert A, Cantoro R, Sauer M, Reorda MS, Becker B (2015) On the automatic generation of SBST test programs for in-field test. Proceedings of 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, pp 1186–1191
Roth JP (1966) Diagnosis of Automata Failures: A Calculus and a method. IBM J Res Dev 10(4):278–291
Sanchez E, Reorda MS (2015) On the Functional Test of Branch Prediction Units. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(9):1675–1688
Schölzel M (2015) Self-Testing and Self-Repairing Embedded Processors: Techniques for statically scheduled superscalar architectures. Habilitation thesis. Brandenburg University of Technology Cottbus-Seftenberg
Shen L, Su S (1988) A Functional Testing Method for Microprocessors. IEEE Trans Comput 37(10):1288–1293
Thatte SM, Abraham JA (1980) Test Generation for Microprocessors. IEEE Trans Comput C-29(6):429–441
Thaker PA, Agrawal VD, Zaghloul ME (2000) Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. Proceedings of International Test Conference 2000 (IEEE Cat. No.00CH37159), Atlantic City, pp 940–949
Ubar R (1980) Fault Diagnosis in Combinational Circuits by Solving Boolean Differential Equations. Autom Remote Control 40(11):part 2. Plenum publishing corporation, USA, pp 1693–1703
Ubar R, Kostin S, Raik J (2012) How to prove that a circuit is Fault-Free?. Proceedings of 2012 15th Euromicro Conference on Digital System Design, Izmir, pp 427–430
van de Goor AJ (1991) Testing Semiconductor memories. Theory and practice. Wiley, New York, p 512
Wang L.-T., Wu Ch.-W., Wen X (2006) VLSI Test Principles and Architectures. Design for testability. Elsevier, pp 777
Wen CH, Wang LC, Cheng K-T (2005) Simulation-based functional test generation for embedded processors. Proceedings of Tenth IEEE International High-Level Design Validation and Test Workshop, Napa Valley, pp 3–10
Zhang Y, Li H, Li X (2013) Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(7):1220–1233
Acknowledgements
The work has been supported by EU’s H2020 project RESCUE, Estonian research grant IUT 19-1, and funded by Excellence Centre EXCITE in Estonia.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: D. Gizopoulos
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Appendices
Appendix A: Theoretical Foundation of The Proposed High-level Control Fault Model
Consider a set F = {fi} of functions, selected as a group of functions to be tested using the fault model of constraints (4) and (5).
Let us define for each function a set of patterns
for which the function fi produces the value yi/k = 0 in the bit k. Let us call the set of patterns D0 (fi/k) as the 0-domain of the function fi for the bit k.
Theorem 1
If for two functions fi/k and fj/k the following D0 {fi/k} − D0 {fj/k} = ∅ is valid, then the fault ri,j/k is functionally redundant.
Proof
From D0 {fi/k} − D0 {fj/k} = ∅ it follows that D0 {fi/k} ⊂ D0 {fj/k}. This means that for each data pattern d ∈ D0 (fi/k), we have yi/k (d) = 0, but also yj/k (d) = 0. Hence, there exists no data which can satisfy the constraint (5), and the functional fault ri,j/k according to Definition 2 is not testable, and is functionally redundant. □
From Theorem 1, the following corollaries straightforwardly result.
Corollary 1
If D0 {fi/k} − D0 {fj/k} = ∅then the difference D0 {fi/k} = D0 {fj/k} is the set of data patterns which can be used for testing the fault ri,j/k.
Corollary 2
If for all bits k, \(D^{0}\left (f_{i / k}\right )-\bigcup _{{j,j\neq i }}D^{0}\left (f_{j / k}\right ) \neq \varnothing \) is valid, then the function fi/k has unique patterns, which produce yi/k = 0 for only the function fi/k and for no one else fj/k, fj ∈ F. Each of these patterns serves as test data for detecting the faults ri,j/k for all fj ∈ F, j≠i.
Corollary 3
If for all bits kD0 {fi/k} − D0 {fj/k} = ∅ is valid, then the function fi is fully distinguishable from the function fj in accordance with the constraints (5), and the functional faults ri,j/k are testable for all bits of k. If all functions fj ∈ F are mutually distinguishable then the set all high-level control faults in M (F) are testable.
In Example 3, we will demonstrate the testability of selected ALU functions in a microprocessor using the proposed high-level control fault model.
Example 3
Consider, as an example, a set of three 1-bit functions f1(OR), f2(AND), and f3(XOR). The truth table of these functions fi and the Venn diagrams of the sets D0 {fi} are illustrated in Fig. 13. According to Venn diagrams, we can notice that there exist the following domains D0 (fi): D0 (OR) = {00}, D0 (AND) = {00, 01, 10}, D0 (XOR) = {00, 11}.
Few examples which illustrate the testability of functions OR, AND, XOR according to Corollaries 1-3, are depicted in Table 1.
Appendix B: Theoretical Foundations for Identification of Not-detectable Low-level Faults in Control Circuits
In the following we provide the main statements and proofs, which justify the identification of the not-detectable (functionally redundant) low-level faults in the real implementation of the given control circuit by its low-level fault simulation using the test T(F) constructed in Section 5.
Theorem 2
The test T (F), which covers all non-redundant high-level faults of the fault model M{F}, covers also all gate-level testable SAF in the control part of the microprocessor, which controls the set of functions F.
Proof
Consider the control part of a MUT presented at high-level in Fig. 3, and described in the real implemented version expanded as the following EDNF as explained in [1], and also in Section 3::
□
Here, the high-level control states si ∈ S used in the formula (1) are mapped into the control signals ci,1ci,2…ci,p of the decoder of the operation code embedded in the instruction of the processor. In [1] and Section 3, it was shown that if all non-redundant appearances of the literals in the EDNF will be tested, then all the non-redundant faults in the original circuit implementation will also be tested. Let us show now, that the high-level test generated for the high-level expression (1) will also test all non-redundant faults in the expression (6).
In the EDNF (6), the variables ci,j for selecting the data results yi,i = 1,…n, represent the global control signals ci,j = 1,…p, which may be either inverted or not, and which cover, in general case, exhaustively all 2p combinations. In the EDNF, due to satisfied constraints (5) of the fault model in Definition 1, when testing the function yi , at least once the value of yj for each i≠j will be yj = 1. On the other hand, due to the exhaustiveness of all 2p combinations of control signals, for each term of EDNF with yi = 1, there will be a combination of control signals ci,1ci,2…ci,p consisting of a single 0, e.g. ci,p = 0, with all others ci,r = 1,r≠p. This is the case, where in the term ci,1ci,2...ci,pyi, the SAF ci,p ≡ 1 is tested. For propagating the fault ci,p ≡ 1 to the output y, all other terms in DNF must have at least one 0 assigned to the variables of the term. This is guaranteed, because due to the constraints (5), which demand that in the term where all cj,k = 1, the value of yj must be 0, and in other terms there must be at least one variable assigned by 0. Hence, all SAF faults of type ci,p ≡ 1 in all variables ci,p can be tested by T (F). The faults ci,p ≡ 0 are tested by test data used in T (F) where the constraint (1) is satisfied. \(\blacksquare \)
Corollary 4
Any gate-level SAF in the control part related to F = {fi}, not detectable by the test T (F) which covers all not redundant high-level control faults of the model M{F}, is redundant.
Proof
In Theorem 2, exhaustiveness of using all the combinations of the local control signals ci,1ci,2…ci,p was assumed. If not all combinations are used in the instruction set of the microprocessor, which is the typical practical case, then, not all patterns can be generated for activating all SAF of type ci,p ≡ 1. Usually these cases are used for optimization of the gate-level structure of the control part of ALU. If however the optimization process has not removed all hardware redundancy, then as the result, the control part may consequently contain also redundant faults. These redundant faults can be identified by simple and fast gate-level fault simulation of the high-level generated test T. □
Rights and permissions
About this article
Cite this article
Oyeniran, A.S., Ubar, R., Jenihhin, M. et al. High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J Electron Test 36, 87–103 (2020). https://doi.org/10.1007/s10836-020-05856-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-020-05856-7