The Booth multipliers require lower number of addition operations compared to the traditional multipliers. Further, higher radix Booth multiplier requires lesser number of adders in its circuit implementation. Multiply and accumulate (MAC) unit plays a crucial role in digital signal processing circuits. Handling the data in area-efficient MAC circuits is challenging since the data word length closely doubles on each multiplication. The data path of higher word length possesses higher hardware complexity. However, such hardware complexity can be minimized by deploying the fixed-width multipliers (FWM) in MAC circuits. In FWMs, the multiplication result of \({{X}_{L-\mathrm{bits}}}\times {{Y}_{L-\mathrm{bits}}}\) is rounded to the higher significant L bits by truncating the rest of lower significant bits. Nevertheless, this truncation introduces the error in multiplication result. This paper presents a radix-8 Booth-based fixed-width signed multipliers with error compensation. Moreover, the estimation of bias value for the error compensation in radix-8 Booth FWM is presented. Accuracy of the fixed-width multiplication with the proposed compensation is analyzed. In addition, the multiplier circuits based on the proposed methods are designed and implemented and the experimental results are discussed.

与传统乘法器相比，Booth乘法器所需的加法运算次数更少。此外，较高的基数展位乘法器在其电路实现中需要较少的加法器数量。乘法和累加（MAC）单元在数字信号处理电路中起着至关重要的作用。在面积高效的MAC电路中处理数据具有挑战性，因为每次乘法时数据字长几乎翻倍。字长较高的数据路径具有较高的硬件复杂性。但是，可以通过在MAC电路中部署固定宽度乘法器（FWM）来最小化此类硬件复杂性。在FWM中，\（{{X} _ {L- \ mathrm {bits}}} \ times {{Y} _ {L- \ mathrm {bits}}} \\的乘法结果四舍五入到较高的有效L通过截断其余的低位有效位。然而，这种截断在乘法结果中引入了误差。本文提出了一种基于基数为8的基于Booth的带误差补偿的定宽有符号乘法器。此外，提出了基数为8的展位FWM中用于误差补偿的偏置值的估计。分析了带有建议补偿的固定宽度乘法的精度。此外，设计并实现了基于所提出方法的乘法器电路，并讨论了实验结果。