Abstract
The Booth multipliers require lower number of addition operations compared to the traditional multipliers. Further, higher radix Booth multiplier requires lesser number of adders in its circuit implementation. Multiply and accumulate (MAC) unit plays a crucial role in digital signal processing circuits. Handling the data in area-efficient MAC circuits is challenging since the data word length closely doubles on each multiplication. The data path of higher word length possesses higher hardware complexity. However, such hardware complexity can be minimized by deploying the fixed-width multipliers (FWM) in MAC circuits. In FWMs, the multiplication result of \({{X}_{L-\mathrm{bits}}}\times {{Y}_{L-\mathrm{bits}}}\) is rounded to the higher significant L bits by truncating the rest of lower significant bits. Nevertheless, this truncation introduces the error in multiplication result. This paper presents a radix-8 Booth-based fixed-width signed multipliers with error compensation. Moreover, the estimation of bias value for the error compensation in radix-8 Booth FWM is presented. Accuracy of the fixed-width multiplication with the proposed compensation is analyzed. In addition, the multiplier circuits based on the proposed methods are designed and implemented and the experimental results are discussed.
Similar content being viewed by others
References
Wang, J.-P.; Kuang, S.-R.; Liang, S.-C.: High-accuracy fixed-width modified Booth multipliers for lossy applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(1), 52–60 (2011)
Min-An, S.; Lan-Da, V.; Sy-Yen, K.: Adaptive low-error fixed-width Booth multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90(6), 1180–1187 (2007)
Li, C.-Y.; Chen, Y.-H.; Chang, T.-Y.; Chen, J.-N.: A probabilistic estimation bias circuit for fixed-width Booth multiplier and its DCT applications. IEEE Trans. Circuits Syste. II Express Br. 58(4), 215–219 (2011)
Jou, S.-J.; Tsai, M.-H.; Tsao, Y.-L.: Low-error reduced-width Booth multipliers for DSP applications. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 50(11), 1470–1474 (2003)
Bewick, G. W.: Fast multiplication: algorithms and implementation. Ph. D. dissertation, Stanford University (1994)
Del Barrio, A.A.; Hermida, R.: A slack-based approach to efficiently deploy radix 8 booth multipliers. in IEEE design, automation & test in Europe conference & exhibition (DATE). 2017, 1153–1158 (2017)
Muralidharan, R.; Chang, C.-H.: Radix-4 and radix-8 Booth encoded multi-modulus multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 60(11), 2940–2952 (2013)
Van, L.-D.; Wang, S.-S.; Feng, W.-S.: Design of the lower error fixed-width multiplier and its application. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(10), 1112–1118 (2000)
Juang, T.-B.; Hsiao, S.-F.: Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Trans. Circuits Syst. II Express Br. 52(6), 299–303 (2005)
Cho, K.-J.; Lee, K.-C.; Chung, J.-G.; Parhi, K.K.: Design of low-error fixed-width modified Booth multiplier. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(5), 522–531 (2004)
Kuang, S.-R.; Wang, J.-P.; Guo, C.-Y.: Modified Booth multipliers with a regular partial product array. IEEE Trans. Circuits Syst. II Express Br. 56(5), 404–408 (2009)
Chen, Y.-H.; Li, C.-Y.; Chang, T.-Y.: Area-effective and power-efficient fixed-width Booth multipliers using generalized probabilistic estimation bias. IEEE J. Emerg. Sel. Top. Circuits Syst. 1(3), 277–288 (2011)
Chen, Y.-H.; Chang, T.-Y.: A high-accuracy adaptive conditional-probability estimator for fixed-width Booth multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 59(3), 594–603 (2012)
Chen, Y.-H.: An accuracy-adjustment fixed-width Booth multiplier based on multilevel conditional probability. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(1), 203–207 (2015)
Jon, S.-J.; Wang, H.-H.: Fixed-width multiplier for DSP application. In: IEEE Proceedings of International conference on computer design, pp. 318–322 (2000)
Jiang, H.; Han, J.; Qiao, F.; Lombardi, F.: Approximate radix-8 Booth multipliers for low-power and high-performance operation. IEEE Trans. Comput. 65(8), 2638–2644 (2016)
Wang, C.-Y.; Kuo, C.-B.; Jou, J.-Y.: Hybrid wordlength optimization methods of pipelined FFT processors. IEEE Trans. Comput. 56(8), 1105–1118 (2007)
Jou, J.M.; Kuang, S.R.; Der Chen, R.: Design of low-error fixed-width multipliers for DSP applications. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 46(6), 836–842 (1999)
Bhusare, S.S.; Kanchana Bhaaskaran, V.: Low-power high-accuracy fixed-width radix-8 Booth multiplier using probabilistic estimation technique. J. Circuits Syst. Comput. 26(5), 1750079 (2016)
Mirhosseini, S.M.; Molahosseini, A.S.; Hosseinzadeh, M.; Sousa, L.; Martins, P.: A reduced-bias approach with a lightweight hard-multiple generator to design a radix-8 modulo \(2^{n}+ 1\) multiplier. IEEE Trans. Circuits Syst. II Express Br. 64(7), 817–821 (2016)
Del Barrio, A.A.; Hermida, R.; Ogrenci-Memik, S.: A combined arithmetic-high-level synthesis solution to deploy partial carry-save radix-8 booth multipliers in datapaths. IEEE Trans. Circuits Syst. I Regul. Pap. 66(2), 742–755 (2018)
Del Barrio, A.A.; Hermida, R.; Memik, S.O.: A partial carry-save on-the-fly correction multispeculative multiplier. IEEE Trans. Comput. 65(11), 3251–3264 (2016)
CIC referenced flow for cell-based IC design, Document no. CIC-DSD-RD-08-01. CHIP implementation center, CIC, Taiwan, Tech. Rep. (2008)
Tang, S.-N.; Tsai, J.-W.; Chang, T.-Y.: A 2.4-GS/s FFT processor for OFDM-based WPAN applications. IEEE Trans. Circuits Syst. II Express Br. 57(6), 451–455 (2010)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Locharla, G.R., Mahapatra, K.K. & Ari, S. Radix-8 Modified Booth Fixed-Width Signed Multipliers with Error Compensation. Arab J Sci Eng 46, 1115–1125 (2021). https://doi.org/10.1007/s13369-020-04920-w
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s13369-020-04920-w