Quantum-dot cellular automata (QCA) is known as one of the best alternative technologies for CMOS on nano-scale dimensions, which allows the design of digital circuits with high speed and density. Decoders are considered as one of the most widely used combinational circuits. They also play an important role in designing circuits such as FPGA, CLB, and memory addressing. In this paper, we propose an effective design of the 2-to-4 decoder in the QCA technology. The proposed design consists of only three inverter gates and six 3-input majority gates. Two single-layer and three-layer of the proposed 2-to-4 QCA decoder with only 56 and 62 cells are provided and they require 3 and 4 clock cycles respectively. Also, one multi-layer 3-to-8 QCA decoder is developed and implemented using the proposed 2-to-4 QCA decoder. The proposed circuits are simulated using the QCADesigner 2.0.3 tool. A comparison of the proposed 2-to-4 QCA decoder with related designs shows that the proposed decoder has a good performance in terms of the number of cells, the occupied area, and the delay criteria. Also, the QCAPro tool is used to compute the power dissipation of the proposed decoder. Finally, the results are affirmed by physical proofs.

中文翻译：

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量子点元胞自动机中高效 2 对 4 解码器的开发

量子点元胞自动机 (QCA) 被称为纳米尺度尺寸 CMOS 的最佳替代技术之一，它允许设计高速和高密度的数字电路。解码器被认为是最广泛使用的组合电路之一。它们还在 FPGA、CLB 和存储器寻址等电路设计中发挥重要作用。在本文中，我们提出了 QCA 技术中 2-to-4 解码器的有效设计。建议的设计仅包含三个反相器门和六个 3 输入多数门。提供了两个单层和三层建议的 2 到 4 QCA 解码器，只有 56 和 62 个单元，它们分别需要 3 和 4 个时钟周期。此外，使用建议的 2 到 4 QCA 解码器开发并实现了一个多层 3 到 8 QCA 解码器。建议的电路使用 QCADesigner 2.0.3 工具进行仿真。将所提出的 2 到 4 QCA 解码器与相关设计的比较表明，所提出的解码器在单元数量、占用面积和延迟标准方面具有良好的性能。此外，QCAPro 工具用于计算建议的解码器的功耗。最后，结果得到物理证明的肯定。