The field of VLSI is evergreen and always growing. Tremendous amount of work is done to embed more gates on a given chip area. This makes it difficult to remove the generated heat. This problem can be solved by using low power circuits. Adiabatic logic style which is advancement over CMOS in terms of power dissipation is a good solution suggested by researchers. In this paper an entirely new approach is presented to address this problem. The proposed circuit dissipates least power as compared to other power saving logic styles. A comparative analysis of all the three logic styles has been presented for better understanding. The circuits are implemented and simulated on Tanner V.13 using 90 nm technology.

VLSI领域是常青树，并且一直在增长。完成了大量工作以在给定的芯片区域上嵌入更多的门。这使得难以除去产生的热量。这个问题可以通过使用低功率电路来解决。研究人员提出，绝热逻辑风格在功耗方面优于CMOS。本文提出了一种全新的方法来解决这个问题。与其他节电逻辑样式相比，拟议的电路消耗的功率最少。为了更好地理解，已经对所有三种逻辑样式进行了比较分析。使用90 nm技术在Tanner V.13上实现和仿真电路。