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A novel low power and highly efficient inverter design

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Abstract

The field of VLSI is evergreen and always growing. Tremendous amount of work is done to embed more gates on a given chip area. This makes it difficult to remove the generated heat. This problem can be solved by using low power circuits. Adiabatic logic style which is advancement over CMOS in terms of power dissipation is a good solution suggested by researchers. In this paper an entirely new approach is presented to address this problem. The proposed circuit dissipates least power as compared to other power saving logic styles. A comparative analysis of all the three logic styles has been presented for better understanding. The circuits are implemented and simulated on Tanner V.13 using 90 nm technology.

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Authors and Affiliations

  1. Electronics and Communication Engineering Department, GGSIPU University, New Delhi, India

    Sapna Sharma, Robinson Devasia & Geetanjali Sharma

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  1. Sapna Sharma
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  2. Robinson Devasia
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  3. Geetanjali Sharma
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Correspondence to Geetanjali Sharma.

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Sharma, S., Devasia, R. & Sharma, G. A novel low power and highly efficient inverter design. Int. j. inf. tecnol. 12, 1111–1116 (2020). https://doi.org/10.1007/s41870-020-00512-x

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  • DOI: https://doi.org/10.1007/s41870-020-00512-x

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