This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.

中文翻译：

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用于低功耗高性能 Booth 乘法器的故障优化电路块

本文介绍了一种利用混合逻辑风格的高性能、全精度布斯乘法器的基本电路块的新颖实现方案。通过利用 MOSFET 寄生电容的特性，采用精心设计的设计风格来降低动态功耗，同时提高电路块的抗干扰能力。电路级技术以及所提出的信号流优化方案可防止部分积和加法器树阶段中虚假活动的产生和传播。通过 65 纳米 CMOS 技术中的广泛布局后模拟，将根据建议的策略构建的两个全精度布斯乘法器与文献中已知的最先进版本进行了比较。