This article describes a 10.7b 300MS/s two-step digital-slope analog-to-digital converter using an on-chip digital-offset correction. The proposed two-step digital-slope ADC is implemented using a passive track-and-hold followed by the input-polarity comparison and the two-step digital-slope conversion. The polarity of the input signal must be determined to control the level-shifting process and specify the operation polarity of the two-step digital-slope conversion. Besides, the two-step digital-slope conversion shares the unary DAC with different weights, which not only mitigates the resolution issues of the digital-slope quantizer but also converts the residue without requiring gain-error calibration. The two-step digital-slope ADC can be divided into three conversion steps and provide 1-bit, 5.7-bit, and 4-bit resolution for each conversion cycle. The digital-offset correction then encodes the three sets of outputs and subtracts the digital-offset caused by the feedback-process latency of the quantizers. The proposed two-step digital-slope ADC is manufactured using 1P9M 65-nm CMOS technology, and the active area of the prototype is 0.0946 square millimeter. At the Nyquist frequency, the SNDR and SFDR measured at 1.2 V, and 300 MS/s are 60.72 dB and 70.05 dB, respectively. With the power consumption of 6.2mW, the corresponding Walden FoM is 23.3 fJ/conversion-step.

中文翻译：

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65nm CMOS 中的 10.7b 300MS/s 两步数字斜率 ADC

本文介绍了使用片上数字偏移校正的 10.7b 300MS/s 两步数字斜率模数转换器。建议的两步数字斜率 ADC 使用无源采样保持，然后是输入极性比较和两步数字斜率转换来实现。必须确定输入信号的极性以控制电平转换过程并指定两步数字斜率转换的操作极性。此外，两步数字斜率转换共享具有不同权重的一元 DAC，这不仅减轻了数字斜率量化器的分辨率问题，而且无需增益误差校准即可转换残差。两步数字斜率 ADC 可分为三个转换步，提供 1 位、5.7 位、和每个转换周期的 4 位分辨率。数字偏移校正然后对三组输出进行编码并减去由量化器的反馈过程延迟引起的数字偏移。拟议的两步数字斜率ADC采用1P9M 65-nm CMOS技术制造，原型的有源面积为0.0946平方毫米。在奈奎斯特频率下，在 1.2 V 和 300 MS/s 下测得的 SNDR 和 SFDR 分别为 60.72 dB 和 70.05 dB。功耗为 6.2mW，对应的 Walden FoM 为 23.3 fJ/conversion-step。原型的有效面积为0.0946平方毫米。在奈奎斯特频率下，在 1.2 V 和 300 MS/s 下测得的 SNDR 和 SFDR 分别为 60.72 dB 和 70.05 dB。功耗为 6.2mW，对应的 Walden FoM 为 23.3 fJ/conversion-step。原型的有效面积为0.0946平方毫米。在奈奎斯特频率下，在 1.2 V 和 300 MS/s 下测得的 SNDR 和 SFDR 分别为 60.72 dB 和 70.05 dB。功耗为 6.2mW，对应的 Walden FoM 为 23.3 fJ/conversion-step。