A micro-programmed Reconfigurable Parallel Finite Impulse Response (RPFIR) filter which can be used as subsystem in wireless sensor node is described in this work. High throughput is achieved using parallel processing and the power consumption is reduced using Vertical Horizontal Binary Common Sub expression Elimination (VHBCSE)-Reconfigurable Multiple Constant Multiplication (RMCM) based multiplier. The logical depth and logical elements are reduced using VHBCSE method. In the existing method, four 8*8 multipliers are used as two operand multiplier in the design of micro-programmed FIR. The two operand multiplier consumes more area and power when compared with Constant Multipliers (CM). The CM has been designed by using only adder, shifters and multiplexers, which consume less area and less power comparing with convention multipliers. The VHBCSE technique is used to find the redundant terms present within and adjutant coefficients, which in turn reduces the number of shifter, adder and multiplexer in the RMCM multiplier. This paper proposes the design of RPFIR filter based on VHBCSE technique which increases the throughput and reduces area and power consumption. It has been found that the power consumption of designed filter is reduced by 28% and throughput is increased by 4 times when compared with the existing FIR filters. Parallel processing used in this proposed system increases the throughput and VHBCSE technique reduces the redundant hardware and power dissipation. Experimental results are obtained for the proposed filter in FPGA platform and ASIC 180 nm technology. Finally, the results are compared with the existing works. The proposed parallel FIR filter will be suitable for implementation of a sensor node in ASIC and FPGA.

这项工作描述了一种微程序可重构并行有限冲激响应（RPFIR）滤波器，该滤波器可用作无线传感器节点中的子系统。使用并行处理可实现高吞吐量，并使用基于垂直水平二进制公共子表达式消除（VHBCSE）-可重配置多重常数乘法（RMCM）的乘法器来降低功耗。使用VHBCSE方法减少了逻辑深度和逻辑元素。在现有方法中，在微程序FIR的设计中，将四个8 * 8乘法器用作两个操作数乘法器。与常数乘法器（CM）相比，两个操作数乘法器消耗更多的面积和功率。CM仅通过使用加法器，移位器和多路复用器进行设计，与常规乘法器相比，它们消耗的面积更少，功耗更低。VHBCSE技术用于查找冗余系数和辅助系数中存在的冗余项，从而减少了RMCM乘法器中的移位器，加法器和多路复用器的数量。本文提出了一种基于VHBCSE技术的RPFIR滤波器设计，该设计提高了吞吐量，减少了面积和功耗。已经发现，与现有的FIR滤波器相比，设计滤波器的功耗降低了28％，吞吐量提高了4倍。在此建议的系统中使用的并行处理可提高吞吐量，而VHBCSE技术可减少冗余硬件和功耗。在FPGA平台和ASIC 180 nm技术下，针对所提出的滤波器进行了实验。最后，将结果与现有作品进行比较。