Recently, multi-FPGA platforms have become a popular choice to prototype complex digital systems. This is because of unique advantages such as high frequency and real world testing experience that are offered when compared to other pre-silicon testing techniques. However, one of several challenges faced by multi-FPGA prototyping is the requirement of an efficient back end flow. Partitioning is a key part of the back end flow of multi-FPGA systems and it directly affects the quality of final prototyped design. In this work, we explore two different partitioning approaches: one is multilevel; while the other is hierarchical partitioning approach. For experimentation, we use a suite of fourteen large benchmarks. Experimental results reveal that the multilevel approach gives 12.5% better frequency results for mono-cluster benchmarks while the hierarchical approach gives 13% better results for multi-cluster benchmarks. Furthermore, the hierarchical approach requires, on average, 60% less execution time when compared to the multilevel partitioning approach.

中文翻译：

---

探索和优化基于多 FPGA 的原型平台的大型设计的划分

最近，多 FPGA 平台已成为复杂数字系统原型的流行选择。这是因为与其他硅前测试技术相比，它具有独特的优势，例如可提供高频和真实世界的测试经验。然而，多 FPGA 原型设计面临的几个挑战之一是需要高效的后端流程。分区是多 FPGA 系统后端流程的关键部分，它直接影响最终原型设计的质量。在这项工作中，我们探索了两种不同的分区方法：一种是多级的；而另一种是分层分区方法。为了进行实验，我们使用了一套 14 个大型基准测试。实验结果表明，多级方法给出了 12。单集群基准测试的频率结果提高了 5%，而分层方法的多集群基准测试的结果提高了 13%。此外，与多级分区方法相比，分层方法平均需要少 60% 的执行时间。