Skip to main content
SpringerLink
Log in

Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms

  • Regular Paper
  • Published:
Computing Aims and scope Submit manuscript

Abstract

Recently, multi-FPGA platforms have become a popular choice to prototype complex digital systems. This is because of unique advantages such as high frequency and real world testing experience that are offered when compared to other pre-silicon testing techniques. However, one of several challenges faced by multi-FPGA prototyping is the requirement of an efficient back end flow. Partitioning is a key part of the back end flow of multi-FPGA systems and it directly affects the quality of final prototyped design. In this work, we explore two different partitioning approaches: one is multilevel; while the other is hierarchical partitioning approach. For experimentation, we use a suite of fourteen large benchmarks. Experimental results reveal that the multilevel approach gives 12.5% better frequency results for mono-cluster benchmarks while the hierarchical approach gives 13% better results for multi-cluster benchmarks. Furthermore, the hierarchical approach requires, on average, 60% less execution time when compared to the multilevel partitioning approach.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Santarini M (2005) Asic prototyping: make versus buy. EDN 11

  2. Sigenics: Custom Asic calculator (2017). http://www.sigenics.com/page/custom-asic-cost-calculator

  3. AMD (2007). http://techreport.com/news/13721/chip-problem-limits-supply-of-quad-core-opterons

  4. Pentium (1994). https://en.wikipedia.org/wiki/pentium_fdiv_bug

  5. Graphics M (2017). https://www.mentor.com/products/fv/modelsim/

  6. Ian Kuon JR (2010) Quantifying and exploring the gap between FPGAs and ASICs. Springer, Berlin

    Book  Google Scholar 

  7. Krupnova H (2004) Mapping multi-million gate SOCS on FPGAS: industrial methodology and experience. In: Proceedings of design, automation and test in Europe conference and exhibition, vol 2, pp 1236–1241 2

  8. Asaad S, Bellofatto R, Brezzo B, Haymes C, Kapur M, Parker B, Roewer T, Saha P, Takken T, Tierno J (2012) A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. In: Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays, ser. FPGA ’12. New York, NY, USA: ACM, pp 153–162. https://doi.org/10.1145/2145694.2145720

  9. Garey MR, Johnson DS (1990) Computers and intractability: a guide to the theory of NPCompleteness. W. H. Freeman & Co., New York

    Google Scholar 

  10. VERIFIC (2019). https://www.verific.com/

  11. Sigl G, Doll K, Johannes F (1991) Analytical placement: a linear or a quadratic objective function? In: Design automation conference, pp 427–432

  12. Alpert CJ, Chan T, Huang D, Kahng A, MarkovI, Mulet P, Yan K (1997) Faster minimization of linear wirelength for global placement. In: ACM symposium on physical design, pp 4–11

  13. Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by simulated annealing. Science 220:671–680

    Article  MathSciNet  Google Scholar 

  14. Sechen C, Sangiovanni-Vincentelli A (1985) The timberwolf placement and routing package. JSSC, pp 510–522

  15. Dunlop A, Kernighan B (1985) A procedure for placement of standard-cell VLSI circuits. In: IEEE transactions on CAD, pp 92–98

  16. Huang D, Kahng A (1997) Partitioning-based standard-cell global placement with an exact objective. In: ACM symposium on physical design, pp 18–25

  17. Kernighan B, Lin S (1970) An efficient heuristic procedure for partitioning graphs. Bell Syst Tech J 49:291–307

    Article  Google Scholar 

  18. Fiduccia CM, Mattheyeses RM (1982) A linear-time heuristic for improving network partitions. In: Design automation conference, pp 175–181

  19. Bui T, Chaudhuri S, Leighton T, Sipser M (1987) Graph bisection algorithms with good average behavior. Combinatorica 7(2):171–191

    Article  MathSciNet  Google Scholar 

  20. Alpert CJ, Hagen LW, Kahng AB (1997) Multilevel circuit partitioning. In: Design automation conference, pp 530–533

  21. Karypis G, Aggarwal R, Kumar V, Shekhar S (1997) Multilevel hypergraph partitioning: application in VLSI design. In: Design automation conference, pp 526–529

  22. Karypis G, Kumar V (1999) Multilevel k-way hypergraph partitioning. In: Design automation conference

  23. Haps protocompiler by synopsys (2017). http://www.synopsys.com/Prototyping/FPGA BasedPrototyping/Pages /protocompiler.aspx

  24. Haps multi-fpga board by synopsys (2017). http://www.synopsys.com/Prototyping/FPGA BasedPrototyping/Pages /HAPS.aspx

  25. Auspy (2017). https://www.mentor.com/products/fv/aupsy

  26. Certify partitioning tool by synopsys (2017). http://www.synopsys.com/Prototyping/FPGA BasedPrototyping/ Pages/Certify.aspx

  27. Series CP (2017). http://www.cadence.com/products/sd/palladium_xp_series/ pages / default.aspx

  28. Veloce MG (2017). https://www.mentor.com/products/fv/emulation-systems/

  29. Zebu-server asic emulator by synopsys (2017). http://www.synopsys.com/tools/verification /hardware-verification/emulation/Pages/default.aspx

  30. Marrakchi Z, Mrabet H, Mehrez H (2005) Hierarchical FPGA clustering to improve routability. In: Conference on Ph.D research in microelectronics and electronics, PRIME

  31. Marrakchi Z, Mrabet H, Mehrez H (2006) A new multilevel hierarchical MFPGA and its suitable configuration tools. In: Proceedings of ISVLSI, Karlsruhe, Germany

  32. Turki M, Mehrez H, Marrakchi Z, Abid M (2013) Partitioning constraints and signal routing approach for multi-fpga prototyping platform. In: 2013 International symposium on system on chip (SoC), pp 1–4

  33. Tang Q, Mehrez H, Tuna M (2013) Routing algorithm for multi-fpga based systems using multi-point physical tracks. In: 2013 International symposium on rapid system prototyping (RSP), pp 2–8

  34. Farooq U, Baig I, Alzahrani BA (2018) An efficient inter-fpga routing exploration environment for multi-fpga systems. IEEE Access 6:56 301–56 310

    Article  Google Scholar 

  35. Inagi M, Takashima Y, Nakamura Y (2009) Globally optimal time-multiplexing in inter-fpga connections for accelerating multi-fpga systems. In: International conference on field programmable logic and applications, pp 212–217

  36. Hauck S, DeHon A (2007) Reconfigurable computing: the theory and practice of FPGA-based computation. Morgan Kaufmann Publishers Inc., San Francisco

    MATH  Google Scholar 

  37. Stroobandt D, Verplaetse P, Van Campenhout J (2000) Generating synthetic benchmark circuits for evaluating cad tools. IEEE Trans Comput Aided Des Integr Circuits Syst 19(9):1011–1022

    Article  Google Scholar 

  38. Farooq U, Parvez H, Mehrez H, Marrakchi Z (2012) A new heterogeneous tree-based application specific fpga and its comparison with mesh-based application specific fpga. Microprocess Microsyst 36(8):588–605. https://doi.org/10.1016/j.micpro.2012.06.012

    Article  Google Scholar 

  39. Yang S (1991) Logic synthesis and optimization benchmarks user guide, version 3.0

  40. Pouillon N, Greiner A (2010) Soc lib project. https://www.asim.lip6.fr/trac/dsx/

  41. Miro Panades I, Greiner A, Sheibanyrad A (2006) A low cost network-on-chip with guaranteed service well suited to the gals approach. In: 1st International conference on nano-networks and workshops, NanoNet ’06, pp 1–5

  42. McMurchie L, Ebeling C (1995) Pathfinder: a negotiation-based performance-driven router for fpgas. In: ACM international symposium on field-programmable gate arrays, ACM Press, New York, pp 111–117

  43. Karypis G, Kumar V (1999) Multilevel k-way hypergraph partitioning. In: Proceedings of the 36th annual ACM/IEEE design automation conference, ser. DAC ’99, ACM, New York, NY, pp 343–348. https://doi.org/10.1145/309847.309954

  44. Synopsys (2017). http://www.synopsys.com/prototyping/fpgabasedprototyping/. http://www.synopsys.com/Prototyping/FPGA BasedPrototyping/FPMM/ Pages/default.aspx

Download references

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, Dhofar University, Salalah, Oman

    Umer Farooq

  2. Faculty of Computing and Information Technology, King Abdulaziz University, Jeddah, Saudi Arabia

    Bander A. Alzahrani

Authors
  1. Umer Farooq
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bander A. Alzahrani
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Umer Farooq.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Farooq, U., Alzahrani, B.A. Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms. Computing 102, 2361–2383 (2020). https://doi.org/10.1007/s00607-020-00834-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00607-020-00834-5

Keywords

Mathematics Subject Classification

Search

Navigation