In this paper, a novel sturcture of planar Silicon on Insulator Junctionless transistor is proposed with improved I_ON/I_OFF ratio, Short Channel effects (SCEs) and most importantly, it is scaleable. A highly doped pocket (p-type) will form PN junction at its interface with n-type channel and hence referred to as pocket doped Silicon on Insulator Junctionless transistor (PD-SOI-JLT). A highly doped region in the channel helps to produce full depletion in the OFF state. A 2D Calibrated simulation study has shown an I_ON/I_OFF ratio 10⁵ in PD-SOI-JLT device comapred to conventional SOI-JLT device for gate length of 20 nm. Further, the use of PN junction isolation reduces the lateral electric field and hence improves the SCE performance of the proposed device as compared to conventional SOI-JLT. Besides this, the ac analysis has shown that the transconductance and Cutoff Frequency of the proposed device is at par with the conventional device.

本文提出了一种新型的绝缘体无结晶体管上的平面硅结构，该结构具有改善的I _ON / I _OFF比，短沟道效应（SCE），最重要的是，它是可缩放的。高掺杂口袋（p型）将在其与n型沟道的界面处形成PN结，因此被称为绝缘体无结晶体管上的口袋掺杂硅（PD-SOI-JLT）。沟道中的高掺杂区有助于在截止状态下产生完全耗尽。二维校准仿真研究显示，对于栅极长度为20 nm的PD-SOI-JLT器件，其I _ON / I _OFF比率为10 ⁵，与常规SOI-JLT器件共映射。此外，使用的PN结隔离减少了横向电场，因此与传统的SOI-JLT相比，提高了所提出器件的SCE性能。除此之外，交流分析表明，该器件的跨导和截止频率与常规器件相当。