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Impact of Pocket Doping On the Performance of Planar SOI Junctionless Transistor

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Abstract

In this paper, a novel sturcture of planar Silicon on Insulator Junctionless transistor is proposed with improved ION/IOFF ratio, Short Channel effects (SCEs) and most importantly, it is scaleable. A highly doped pocket (p-type) will form PN junction at its interface with n-type channel and hence referred to as pocket doped Silicon on Insulator Junctionless transistor (PD-SOI-JLT). A highly doped region in the channel helps to produce full depletion in the OFF state. A 2D Calibrated simulation study has shown an ION/IOFF ratio 105 in PD-SOI-JLT device comapred to conventional SOI-JLT device for gate length of 20 nm. Further, the use of PN junction isolation reduces the lateral electric field and hence improves the SCE performance of the proposed device as compared to conventional SOI-JLT. Besides this, the ac analysis has shown that the transconductance and Cutoff Frequency of the proposed device is at par with the conventional device.

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Authors and Affiliations

  1. Department of Electronics and Instrumentation Technology, University of Kashmir, Srinagar J&K, India

    Faisal Bashir, Farooq A. Khanday & Mohammad Tariq Banday

  2. Computer Department, College of Science, Kirkuk University, Kirkuk, Iraq

    Asim M. Murshid

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  1. Faisal Bashir
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  2. Asim M. Murshid
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  3. Farooq A. Khanday
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  4. Mohammad Tariq Banday
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Correspondence to Faisal Bashir.

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Bashir, F., Murshid, A.M., Khanday, F.A. et al. Impact of Pocket Doping On the Performance of Planar SOI Junctionless Transistor. Silicon 13, 1771–1776 (2021). https://doi.org/10.1007/s12633-020-00568-1

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  • DOI: https://doi.org/10.1007/s12633-020-00568-1

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