In this letter, we present a two-stage rail-to-rail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NOR-based synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator has reduced the delay by 2–11\(\times\), reduced the standard deviation of offset by 1.09–1.39\(\times\), and reduced the power consumption up to 3.80\(\times\) compared to the NAND–&NOR-based comparator. Hence, these improvements can be used to further advance the performance of all-digital synthesizable design circuits.

在这封信中，我们介绍了两级轨至轨完全可合成的动态电压比较器。为了提高基于NAND和NOR的可合成比较器的速度和失配性能，我们建议分别用OAI和AOI逻辑门代替这些逻辑。该比较器采用CMOS 45 nm技术实现，在350 mV至1.0 V的电源电压下工作。拟议的比较器将延迟降低了2–11 \（\ times \），将偏移的标准偏差降低了1.09–1.39 \（\ times \），与NAND –＆NOR相比，功耗降低了3.80 \（\ times \）基于的比较器。因此，这些改进可用于进一步提高全数字可合成设计电路的性能。