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A 0.35 V-to-1.0 V synthesizable rail-to-rail dynamic voltage comparator based OAI&AOI logic

  • Mixed Signal Letter
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Abstract

In this letter, we present a two-stage rail-to-rail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NOR-based synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator has reduced the delay by 2–11\(\times\), reduced the standard deviation of offset by 1.09–1.39\(\times\), and reduced the power consumption up to 3.80\(\times\) compared to the NAND–&NOR-based comparator. Hence, these improvements can be used to further advance the performance of all-digital synthesizable design circuits.

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Acknowledgements

This research is supported in part by the National Key Research and Development Program of China under Grant No. 2019YFB2204500 and in part by the Science, Technology and Innovation Action Plan of Shanghai Municipality, China under Grant No. 1914220370.

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Authors and Affiliations

  1. Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, 200240, China

    Xiaocui Li, Ting Zhou, Yuxin Ji & Yongfu Li

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  1. Xiaocui Li
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  2. Ting Zhou
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  4. Yongfu Li
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Correspondence to Yongfu Li.

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Li, X., Zhou, T., Ji, Y. et al. A 0.35 V-to-1.0 V synthesizable rail-to-rail dynamic voltage comparator based OAI&AOI logic. Analog Integr Circ Sig Process 104, 351–357 (2020). https://doi.org/10.1007/s10470-020-01682-1

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