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A highly programmable 60-dB gain analog baseband circuit with DC-offset cancellation for short-range FMCW radar applications
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2020-06-29 , DOI: 10.1007/s10470-020-01679-w
Dušan V. Obradović , Ðorđe P. Glavonjić , Dušan P. Krčum , Veljko R. Mihajlović , Ivan M. Milosavljević

This paper presents a fully integrated analog baseband circuit with high reconfigurability intended for use in short-range frequency-modulated continuous-wave (FMCW) radar sensors. The fully differential baseband circuitry achieves maximum overall gain of 60 dB which is adjustable with a 3-dB step. Second-order high-pass filter and fifth-order low-pass filter are incorporated in chain and possess tunable cutoff frequencies in the range 0.1–1 MHz and 0.25–1.3 MHz, respectively. They are adjustable with high accuracy, yielding simultaneously the rejection of undesired signals and neglecting the effects from process, voltage, and temperature variations. In order to enhance baseband circuit utilization and flexibility for radar’s targets with various proximities and velocities, two operating modes are proposed for low noise and high linearity. Simulated at maximum gain setting, it achieves an in-band third-order input intercept point of \(-17\,\text {dBm}\) and an input-referred noise of 6.5 or \(14.7\,{\text {nV}}/\sqrt{{\text {Hz}}}\) depending on operating mode. Furthermore, DC offset cancellation circuit is incorporated in baseband chain. Implemented in a commercially available 130-nm SiGe BiCMOS process technology, as part of the large FMCW transceiver chip, it occupies the area of \(0.36\,{\text {mm}}^2\) and consumes 30 or \(33\,{\text {mW}}\) in low-noise or high-linearity modes, respectively.



中文翻译:

高度可编程的60 dB增益模拟基带电路,具有DC抵消功能,适用于短距离FMCW雷达应用

本文提出了一种具有高可重构性的全集成模拟基带电路,旨在用于短程调频连续波(FMCW)雷达传感器。全差分基带电路可实现60dB的最大总增益,该增益可通过3dB的步长进行调节。二阶高通滤波器和五阶低通滤波器被并入链中,并分别具有0.1-1 MHz和0.25-1.3 MHz范围内的可调截止频率。它们具有很高的精度,可以同时抑制不想要的信号,而忽略了过程,电压和温度变化的影响。为了提高基带电路的利用率和具有各种接近度和速度的雷达目标的灵活性,针对低噪声和高线性度提出了两种工作模式。\(-17 \,\ text {dBm} \)和6.5或\(14.7 \,{\ text {nV}} / \ sqrt {{\ text {Hz}}} \\的输入参考噪声,具体取决于操作模式。此外,DC偏移消除电路被并入基带链中。作为大型FMCW收发器芯片的一部分,采用可商购的130纳米SiGe BiCMOS工艺技术实现,它占用\(0.36 \,{\ text {mm}} ^ 2 \)的面积,消耗30或\(33 \,{\ text {mW}} \)分别在低噪声或高线性模式下。

更新日期:2020-06-29
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