A distinctive charge plasma approach is used to propose a novel dual-metal-gate (DMG) recessed-source/drain dopingless junctionless transistor (Re S/D DLJLT) in which the source/drain (S/D) series resistance is reduced without any increment of the gate-to-drain Miller capacitance. In this device, the charge plasma approach is applied to induce an N⁺ (virtually doped) S/D region by using metals with appropriate work functions for the electrodes. The direct-current (DC) and analog/radio frequency (RF) figures of merit (FOMs) of the proposed device are analyzed using two-dimensional (2-D) numerical calculations and compared with those for a DMG recessed-source/drain junction transistor (Re S/D JT) of identical dimensions. The results reveal that the DMG-Re S/D DLJLT exhibits enhanced DC and analog/RF performance compared with the DMG-Re S/D JT. The total gate length (L) is divided between the control gate (L₁) and screen gate (L₂), and the numerical investigations are carried out with different ratios of the control gate to screen gate lengths (L₁:L₂) to determine the optimized gate length for the DMG. A subthreshold slope of 61.32 mV/dec is obtained for the proposed device with L₁:L₂ = 1:1. An improvement in the ON-state current (I_ON) is observed due to the introduction of the charge plasma concept, which also reduces the OFF-state leakage current (I_OFF) and causes a net enhancement in the I_ON/I_OFF ratio. The device proposed herein also solves the problems of random doping fluctuation, doping activation, and threshold voltage variation and may thus be preferred over DMG-Re S/D JTs for use in analog/RF and digital applications due to its improved performance.

中文翻译：

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基于电荷等离子的双金属栅嵌入式源极/漏极无掺杂无结晶体管，具有增强的模拟和RF性能

一种独特的电荷等离子体方法被用于提出一种新颖的双金属栅（DMG）内隐源极/漏极无掺杂无结晶体管（Re S / D DLJLT），其中源极/漏极（S / D）串联电阻减小而栅漏米勒电容的任何增量。在该设备中，采用电荷等离子体方法来感应N ⁺（使用虚拟掺杂）S / D区，方法是使用对电极具有适当功函数的金属。使用二维（2-D）数值计算分析了所建议设备的直流（DC）和模拟/射频（RF）品质因数（FOM），并与DMG隐式源/漏的那些进行了比较。尺寸相同的结型晶体管（Re S / D JT）。结果表明，与DMG-Re S / D JT相比，DMG-Re S / D DLJLT具有增强的DC和模拟/ RF性能。将总栅极长度（L）分为控制栅极（L ₁）和屏蔽栅极（L ₂），并使用不同比例的控制栅极与屏蔽栅极长度（L _1）进行数值研究。：L ₂）来确定DMG的最佳栅极长度。对于拟议的器件，L ₁：L ₂  = 1：1可获得亚阈值斜率61.32 mV / dec 。由于引入了电荷等离子体概念，因此观察到导通状态电流（I _ON）有所改善，这也降低了截止状态漏电流（I _OFF）并导致I _ON / I _OFF的净增加比。本文提出的装置还解决了随机掺杂波动，掺杂激活和阈值电压变化的问题，并且由于其改进的性能，因此在模拟/ RF和数字应用中可能比DMG-Re S / D JT更可取。