Abstract
A distinctive charge plasma approach is used to propose a novel dual-metal-gate (DMG) recessed-source/drain dopingless junctionless transistor (Re S/D DLJLT) in which the source/drain (S/D) series resistance is reduced without any increment of the gate-to-drain Miller capacitance. In this device, the charge plasma approach is applied to induce an N+ (virtually doped) S/D region by using metals with appropriate work functions for the electrodes. The direct-current (DC) and analog/radio frequency (RF) figures of merit (FOMs) of the proposed device are analyzed using two-dimensional (2-D) numerical calculations and compared with those for a DMG recessed-source/drain junction transistor (Re S/D JT) of identical dimensions. The results reveal that the DMG-Re S/D DLJLT exhibits enhanced DC and analog/RF performance compared with the DMG-Re S/D JT. The total gate length (L) is divided between the control gate (L1) and screen gate (L2), and the numerical investigations are carried out with different ratios of the control gate to screen gate lengths (L1:L2) to determine the optimized gate length for the DMG. A subthreshold slope of 61.32 mV/dec is obtained for the proposed device with L1:L2 = 1:1. An improvement in the ON-state current (ION) is observed due to the introduction of the charge plasma concept, which also reduces the OFF-state leakage current (IOFF) and causes a net enhancement in the ION/IOFF ratio. The device proposed herein also solves the problems of random doping fluctuation, doping activation, and threshold voltage variation and may thus be preferred over DMG-Re S/D JTs for use in analog/RF and digital applications due to its improved performance.
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The authors would like to express their honest thanks to the VLSI laboratory of MNNIT Allahabad, for providing resources to use SILVACO TCAD for numerical investigation of the device structures.
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Verma, P.K., Verma, Y.K., Mishra, V. et al. A charge-plasma-based dual-metal-gate recessed-source/drain dopingless junctionless transistor with enhanced analog and RF performance. J Comput Electron 19, 1085–1099 (2020). https://doi.org/10.1007/s10825-020-01528-z
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DOI: https://doi.org/10.1007/s10825-020-01528-z