There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.

中文翻译：

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工业后硅验证中系统裕度和抖动容限优化的整体公式

微处理器和片上系统 (SoC) 中混合信号电路的数量越来越多。其中很大一部分对应于高速输入/输出 (HSIO) 链路。HSIO 链路的硅后验证对于在积极的发布时间表下做出产品发布资格决定至关重要。现代 HSIO 链路中接收器模拟电路的优化是一个非常耗时的后硅验证过程。当前的工业实践基于详尽的枚举方法，以提高系统裕度或抖动容限一致性测试。在本文中，这两个要求在基于整体优化的方法中得到解决。我们基于这两个指标提出了一个新的目标函数。我们的方法采用克里金法来构建基于系统裕度和抖动容限测量的替代模型。所提出的方法通过三个不同的实际服务器 HSIO 链路进行测试，能够提供最佳系统裕度并保证抖动容限合规性，同时显着减少典型的后硅验证时间。