This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single transistor. According to Simulations using HSPICE software in 10 nm FinFET technology, the read stability of the proposed cell is approximately 4.8× higher than the conventional 6T at 200 mV. Furthermore, the proposed cell is found to have the lowest static power dissipation, as it tends to be 4% lower than the standard six-transistor cell at this voltage. This study shows that the yield of the proposed cell is higher than 6σ in all operations, and supply voltages down to 200 mV.

本文在亚阈值区域展示了一种低泄漏功率的10T单端SRAM单元，该单元提高了读取，写入和保持的稳定性。在低电压下，通过暂时使数据节点浮置来提高可写性，而通过仅使用单个存储单元将数据存储节点与读取位线分开，则可以将单元的读取稳定性保持为近似等于保持状态晶体管。根据在10 nm FinFET技术中使用HSPICE软件进行的仿真，在200 mV电压下，所建议单元的读取稳定性比传统6T高约4.8倍。此外，发现拟议的电池具有最低的静态功耗，因为在此电压下它往往比标准的六晶体管电池低4％。这项研究表明，所提出的细胞产率高于6σ 在所有操作中，电源电压低至200 mV。