Skip to main content
Log in

A single-ended low leakage and low voltage 10T SRAM cell with high yield

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single transistor. According to Simulations using HSPICE software in 10 nm FinFET technology, the read stability of the proposed cell is approximately 4.8× higher than the conventional 6T at 200 mV. Furthermore, the proposed cell is found to have the lowest static power dissipation, as it tends to be 4% lower than the standard six-transistor cell at this voltage. This study shows that the yield of the proposed cell is higher than 6σ in all operations, and supply voltages down to 200 mV.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Ahmad, S., Alam, N., & Hasan, M. (2018). Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications. AEU: International Journal of Electronics and Communications, 83, 366–375.

    Google Scholar 

  2. Singh, A. K., Saadatzi, M., & Venkataseshaiah, C. (2017). Design of a single-ended energy efficient data-dependent-write-assist dynamic (DDWAD) SRAM cell for improved stability and reliability. Analog Integrated Circuits and Signal Processing, 90(2), 411–426.

    Article  Google Scholar 

  3. Singh, A. K., Seong, M. M., & Prabhu, C. M. R. (2014). A data aware 9T static random access memory cell for low power consumption and improved stability. International Journal of Circuit Theory and Applications, 42(9), 956–966.

    Article  Google Scholar 

  4. Saeidi, R., Sharifkhani, M., & Hajsadeghi, K. (2014). Statistical analysis of read static noise margin for near/sub-threshold SRAM cell. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(12), 3386–3393.

    Article  Google Scholar 

  5. Manju, I., & Senthil Kumar, A. (2015). A 22 nm FinFET based 6T-SRAM cell design witah scaled supply voltage for increased read access time. Analog Integrated Circuits and Signal Processing, 84(1), 119–126.

    Article  Google Scholar 

  6. Zeinali, B., Madsen, J. K., Raghavan, P., & Moradi, F. (2017). Low-leakage sub-threshold 9 T-SRAM cell in 14 nm FinFET technology. International Journal of Circuit Theory and Applications, 45(11), 1647–1659.

    Article  Google Scholar 

  7. Jeong, H., Oh, S. H., Oh, T. W., Kim, H., Park, C. N., Rim, W., et al. (2019). Bitline charge-recycling SRAM write assist circuitry for V MIn improvement and energy saving. IEEE Journal of Solid-State Circuits, 54(3), 896–906.

    Article  Google Scholar 

  8. Chang, L., Fried, D. M., Hergenrother, J., Sleight, J. W., Dennard, R. H., Montoye, R. K., & Guarini, K. W. (2005, June). Stable SRAM cell design for the 32 nm node and beyond. In Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. (pp. 128–129). IEEE.

  9. Yueh, W., Chatterjee, S., Zia, M., Bhunia, S., & Mukhopadhyay, S. (2015). A memory-based logic block with optimized-for-read SRAM for energy-efficient reconfigurable computing fabric. IEEE Transactions on Circuits and Systems II: Express Briefs, 62(6), 593–597.

    Article  Google Scholar 

  10. Jeon, D., Dong, Q., Kim, Y., Wang, X., Chen, S., Yu, H., et al. (2017). A 23 mW Face Recognition Processor with Mostly-Read 5T Memory in 40 nm CMOS. IEEE Journal of Solid-State Circuits, 52(6), 1628–1642.

    Article  Google Scholar 

  11. Saxena, S., & Mehra, R. (2017). Low-power and high-speed 13T SRAM cell using FinFETs. IET Circuits Devices and Systems, 11(3), 250–255.

    Article  Google Scholar 

  12. Pasandi, G., & Fakhraie, S. M. (2014). An 8t low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs. IEEE Transactions on Electron Devices, 61(7), 2357–2363.

    Article  Google Scholar 

  13. Pasandi, G., & Pedram, M. (2018). Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs. IET Circuits Devices and Systems, 12(4), 460–466.

    Article  Google Scholar 

  14. Predictive Technology Model (PTM). (2007). Nanoscale Integration and Modeling (NIMO) Group. Retrieved from http://ptm.asu.edu/.

  15. Ingerly, D., Agrawal, A., Ascazubi, R., Blattner, A., Buehler, M., Chikarmane, V., & Glassman, T. (2012, June). Low-k interconnect stack with metal-insulator-metal capacitors for 22 nm high volume manufacturing. In 2012 IEEE International Interconnect Technology Conference (pp. 1–3). IEEE.

  16. Ansari, M., Afzali-Kusha, H., Ebrahimi, B., Navabi, Z., Afzali-Kusha, A., & Pedram, M. (2015). A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. Integration, The VLSI Journal, 50, 91–106.

    Article  Google Scholar 

  17. Anitha, D., Manjunathachari, K., Sathish Kumar, P., & Prasad, G. (2017). Design of low leakage process tolerant SRAM cell. Analog Integrated Circuits and Signal Processing, 93(4), 1–8.

    Google Scholar 

  18. Mishra, J. K., Srivastava, H., Misra, P. K., & Goswami, M. (2019). Analytical modelling and design of 9T SRAM cell with leakage control technique. Analog Integrated Circuits and Signal Processing, 101(1), 31–43.

    Article  Google Scholar 

  19. Makino, H., Nakata, S., Suzuki, H., Mutoh, S., Miyama, M., Yoshimura, T., et al. (2011). Reexamination of SRAM cell write margin definitions in view of predicting the distribution. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(4), 230–234.

    Article  Google Scholar 

  20. Lorenzo, R., & Chaudhury, S. (2017). A novel 9T SRAM architecture for low leakage and high performance. Analog Integrated Circuits and Signal Processing, 92(2), 315–325.

    Article  Google Scholar 

  21. Sharma, V., Gopal, M., Singh, P., Vishvakarma, S. K., & Chouhan, S. S. (2019). A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications. Analog Integrated Circuits and Signal Processing, 98(2), 331–346.

    Article  Google Scholar 

  22. Salahuddin, S., Jiao, H., & Kursun, V. (2013, March). A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. In International Symposium on Quality Electronic Design (ISQED) (pp. 353–358). IEEE.

  23. Kushwah, C. B., & Vishvakarma, S. K. (2016). A single-ended with dynamic feedback control 8T subthreshold SRAM cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(1), 373–377.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Behzad Ebrahimi.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Eslami, N., Ebrahimi, B., Shakouri, E. et al. A single-ended low leakage and low voltage 10T SRAM cell with high yield. Analog Integr Circ Sig Process 105, 263–274 (2020). https://doi.org/10.1007/s10470-020-01669-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-020-01669-y

Keywords

Navigation