In this paper, we propose a low-power yet area-efficient fault tolerant adder by using Berger codes. The proposed Berger code checker is designed by using the current mode multi-valued logic (CM-MVL) circuits. The proposed structure, which is more area and power efficient than state-of-the-art fault tolerant adders, is able to detect all single and multi-bit unidirectional faults. The efficiency of the proposed fault tolerant adder is evaluated by comparing its characteristics to those of two state-of-the-art fault detection schemes in adders as well as the conventional duplex and parity bit checkers in a 90 nm technology. The results reveal that the proposed 64-bit Berger code checker for adders imposes up to 6.7% and 27.2% delay and area penalties, respectively with a cost of static power dissipation. In the proposed scheme, in sub threshold regime, the power penalty is just 1%, while its area overhead is only 31%. The drawback of using this scheme in sub threshold regime is that delay time introduced to the circuit is unacceptable. So, depending on the application, we should choose one of the above-mentioned schemes.

中文翻译：

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电流模式多值逻辑中的低功耗区域高效容错加法器使用 Berger 码

在本文中，我们通过使用 Berger 代码提出了一种低功耗但面积高效的容错加法器。所提出的 Berger 代码检查器是通过使用电流模式多值逻辑 (CM-MVL) 电路设计的。所提出的结构比最先进的容错加法器具有更大的面积和功率效率，能够检测所有单位和多位单向故障。通过将其特性与加法器中两种最先进的故障检测方案以及 90 nm 技术中的传统双工和奇偶校验位检查器的特性进行比较，评估了所提出的容错加法器的效率。结果表明，所提议的用于加法器的 64 位 Berger 代码检查器分别施加了高达 6.7% 和 27.2% 的延迟和面积损失，并以静态功耗为代价。在提议的方案中，在低于阈值的情况下，功率损失仅为 1%，而其面积开销仅为 31%。在亚阈值机制中使用该方案的缺点是引入电路的延迟时间是不可接受的。因此，根据应用，我们应该选择上述方案之一。