Abstract

The parallel automaton is considered which is the functional model of a discrete control device which allows taking into account the parallel character of logical control devices. The verification of parallel automata lies in testing all transitions in the graph of the complete states of automata and is conducted based on simulation. The software tools for constructing the compact tests for verifying the parallel automaton and for obtaining the VHDL model of parallel automata aimed at implementing their scheme are proposed. The obtained algorithmic VHDL models of the automata are synthesizable, which allows obtaining the scheme implementations of parallel automata in various design libraries.

中文翻译：

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并行自动机的验证与方案实现

摘要

并行自动机被认为是离散控制设备的功能模型，它允许考虑逻辑控制设备的并行特性。并行自动机的验证在于测试自动机完整状态图中的所有转换，并且是基于仿真进行的。提出了构建用于验证并行自动机的紧凑测试并获得并行自动机的VHDL模型的软件工具，旨在实现其方案。所获得的自动机的算法VHDL模型是可合成的，从而允许在各种设计库中获得并行自动机的方案实现。