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Verification and Scheme Implementation of Parallel Automata

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Abstract

The parallel automaton is considered which is the functional model of a discrete control device which allows taking into account the parallel character of logical control devices. The verification of parallel automata lies in testing all transitions in the graph of the complete states of automata and is conducted based on simulation. The software tools for constructing the compact tests for verifying the parallel automaton and for obtaining the VHDL model of parallel automata aimed at implementing their scheme are proposed. The obtained algorithmic VHDL models of the automata are synthesizable, which allows obtaining the scheme implementations of parallel automata in various design libraries.

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REFERENCES

  1. Polyakov, A.K., Yazyki VHDL i VERILOG v proektirovanii tsifrovoi apparatury (VHDL and VERILOG Languages in the Design of Digital Equipment), Moscow: SOLON-Press, 2003.

    Google Scholar 

  2. Bibilo, P.N. and Avdeev, N.A., Modelirovanie i verifikatsiya tsifrovykh sistem na yazyke VHDL (Modeling and Verification of Digital Systems in VHDL), Moscow: LENAND, 2017.

    Google Scholar 

  3. Khakhanov, V.I., Khakhanova, I.V., Litvinova, E.I., and Guz’, O.A., Proektirovanie i verifikatsiya tsifrovykh sistem na kristallakh. Verilog and SystemVerilog (Design and Verification of Digital Systems on Crystals. Verilog and SystemVerilog), Kharkov: KhNURE, 2010.

  4. SystemVerilog 3.1a. Language Reference Manual. http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_ 3.1a.pdf

  5. Eisner, C. and Fismam, D., A Practical Introduction to PSL, New York: Springer, 2006.

    Google Scholar 

  6. Chen, M., Qin, X., Koo, H.-M., and Mishra, P., System-Level Validation: High-Level Modeling and Directed Test Generation Techniques, New York: Springer, 2013.

    Book  Google Scholar 

  7. Yankin, Yu.Yu. and Shalyto, A.A., Redundant electric motor drive control unit design using automata-based approach, Nauch.-Tekh. vestn. Inform. Tekhnol. Mekh. Opt., 2014, no. 6(94), pp. 146–152.

  8. Lokhov, A. and Rabovolyuk, A., Complex functional VLSI verification mentor graphic’s Questa, Elektron.: Nauka, Tekhnol., Biznes, 2007, no. 3, pp. 102–109.

  9. Zakrevskii, A.D., Parallel’nye algoritmy logicheskogo upravleniya (Parallel Logic Control Algorithms), Minsk: Inst. Tekhn. Kibernet. NAN Belarusi, 1999.

  10. Zakrevskii, A.D., Pottosin, Yu.V., and Cheremisinova, L.D., Logicheskie osnovy proektirovaniya diskretnykh ustroistv (The Logic Bases of Discrete Device Design), Moscow: Fizmatlit, 2007.

  11. Burdonov, I.B., Kosachev, A.S., Ponomarenko, V.N., and Shnitman, V.Z., Overview of distributed systems verification approaches, Preprint no. 16, Moscow: Inst. Sist. Programmir. RAN, 2003. www.ispras.ru/preprints/ docs/prep_16_2006.pdf.

    Google Scholar 

  12. Bibilo, P.N. and Romanov, V.I., Building compact tests for functional verification of VHDL-descriptions of finite state machines, Upravl. Sist. Mashiny, 2017, no. 1, pp. 35–45.

  13. Vityaz’, K.A. and Romanov, V.I., Algorithms for constructing functional tests for a digital circuit based on an automaton model of its behavior, in Tanaevskie chteniya, Doklady Vos’moi Mezhdunarodnoi nauchnoi konferentsii (Proceedings of the 8th International Conference Tanaev Readings, March 27–30, 2018, Minsk), Minsk: OIPI NAN Belarusi, 2018, pp. 52–56.

  14. Bibilo, P.N., Sistemy proektirovaniya integral’nykh skhem na osnove yazyka VHDL. StateCAD, ModelSim, LeonardoSpectrum (Design Systems for Integrated Circuits Based on the VHDL Language. StateCAD, ModelSim, LeonardoSpectrum), Moscow: SOLON-Press, 2005.

  15. Shlee, M., Qt5.3. Professional’noe programmirovanie na C++ (Qt 5.3. Professional Programming in C++), St. Petersburg: BKhV-Peterburg, 2015.

  16. Kamkin, A.S., Projecting transition systems: overcoming state explosion in concurrent system verification, Programm. Comput. Software, 2015, vol. 41, no. 6, pp. 311–324.

    Article  MathSciNet  Google Scholar 

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Authors and Affiliations

  1. United Institute of Informatics Problems, National Academy of Sciences of Belarus, 220012, Minsk, Belarus

    N. A. Avdeev, P. N. Bibilo & V. I. Romanov

Authors
  1. N. A. Avdeev
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  2. P. N. Bibilo
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  3. V. I. Romanov
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Corresponding authors

Correspondence to P. N. Bibilo or V. I. Romanov.

Additional information

Translated by E. Oborin

Abbreviations: VLSI, very-large-scale integrated circuits; PLIC, programmable logic integrated circuits; CAD, computer-aided design systems; PRALU, Simple Logic Control Algorithms; PLM, programmable logic matrix.

APPENDIX 1

APPENDIX 1

VHDL-description of ZAK178 parallel automaton

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Avdeev, N.A., Bibilo, P.N. & Romanov, V.I. Verification and Scheme Implementation of Parallel Automata. Russ Microelectron 49, 62–75 (2020). https://doi.org/10.1134/S1063739719060027

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  • DOI: https://doi.org/10.1134/S1063739719060027

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